Orange Squeezer tidbit: what to aim for with the trimpot

[Mark Hammer]

I was perusing through a pile of old Japanese schematics instead of working like I should be, and noticed something called an "Orange Clash".  On closer inspection it was very clearly a note-for-note/part-for-part clone of an Orange Squeezer.  Although the accompanying text is in Japanese (which is Greek to me!), the schematic shows an arrow pointing to the place where the trimpot, 24k resistor, 4u7 cap and gate of the secondary FET are tied to the source of the principle FET.  The schematic indicates that, with a 9v supply, this trimpot should be adjusted to read between +1.5 and +1.7vdc.  Obviously you can take that reading at any of the aforementioned components where your probe conveniently fits.

It also indicates a DC reading of +4.9V on the output pin of the op-amp, just before the 4u7 output cap, and a probable peak envelope amplitude of around 1.7V where the diode meets the 470k and 100k resistors.

Just thought those voltages would be helpful for debugging for some folks here.

[claytushaywood]

just found this... ill try it, but did you mean 2.4k resistor?  I havent found an OS layout with a 24k resistor or anything close!

[smolder]

fwiw - with a IC NE5532 I was unable to get sound below 1.96 volts, and it sounded good at about 2.02., so I left it there.

[GGBB]

Thanks Mark.  I am planning an OS as my next build, so this will definitely come in handy.

[rankot]

I've built an Orange Squeezer, but I have a problem - whatever I try, I get very distorted sound. Does anybody have any hint?

[GGBB]

Distorted sound can be a symptom of improper bias adjustment. Can you elaborate on "whatever I try" - what all have you tried?

[rankot]

Regardless how I turn bias pot - minimium and maximum and all the possitions in between produce the same sound Is there a specific value range for Vgs(off) or Idss for 2N5457 JFET used here? Or maybe the problem is in a fact that I have used TL074 IC?

[GGBB]

You'll need to do some debugging. Go to the top of the byos section and read the sticky debugging thread. You need to also check that the trim pot is actually changing the voltages on the JFETs. A TL074 should be fine as long as it is connected properly. Specs for the 2N5457 can be found in the spec sheet.

[rankot]

Well, I have the spec sheet for 2N5457, but their Vgs values vary a lot, so maybe this value could be critical for OS to work well. I asked if someone has an idea of usable Vgs range for OS. I'll try to debug.

[GGBB]

You're right - there is a lot of variance in jfet specs. The trimpot in the OS is intended to deal with that issue, but it is possible that the FETs you have are too far towards the end of the range to work properly. So that leads to debugging.

[rankot]

OK, so let's try with debugging. I used this schematic:


DC voltage after protection diode is 8.80V.

Now, I first used 10k trim pot to bias the pedal, but I couldn't bias Q1 gate voltage very fine, it started to change at trim value lowered almost at 0. Doing that, I fried Q1. So I replaced Q1 and soldered 1k2 resistor in series with trim, and then I could get 6.4V on Q1 gate when trim is at 0. Then I have measured voltages on IC pins, as follows:
1 - 4.69V
2 - 4.72V
3 - 4.62V
4 - 0.00V
5 - 8.69V
6 - 8.10V
7 - 8.09V
8 - 0.25V
After that, I tried to solder 20 ohm resistor in series with bias trim, but it burned after one minute with trim pot set to 0. I tried 10 ohm resistor and it gives 4.00V at Q1 gate, but it is getting hot pretty fast, so I had to turn it off!

[rankot]

Putting 100 ohm resistor instead of bias trim gives 5.84V at Q1 gate.

[Rob Strand]

rankot, what you are seeing points to a problem. 
Check you have the correct pin-outs for the JFETs.
Also check your 2.4k is in fact 2.4k by measuring it.

On the subject of biasing,  you cannot set the bias point reliably using voltage measurements
as the JFET part to part variation is too high. 

One "production-line compatible" way to set the bias is the  put a 1kHz sine-wave into the input
then adjust the bias until the ac output of the first opamp is a certain value.  I can't remember the
numbers.

[slacker]

OK, so let's try with debugging. I used this schematic:

There's something wrong with that schematic, there needs to be a capacitor between lug 2 of the level pot and where R13, R14 and pin 5 of the opamp connect, a 47n or larger cap will work fine. Without it IC1B won't be properly biased and will distort even if the FETs are biased correctly.

[rankot]

Thanks to everyone! I will try to add that coupling capacitor before the 2nd op amp. Also, I have measured R4 and it is almost exactly 2k4, and I have checked C4, and it is also fine. But Rob was right - I rotated FETs for 180 degrees 

Now, I turned them as they should be, and when I turn 10k trimpot to max, I get some 0.8V at Q1 gate, turning it lower makes that value lower. I will try with 100K pot and report what happens. Now, no sound at all...

[rankot]

I am able to bias JFET right now, so when I set Q1 gate to 1.6V, OS can work, but the sound is still distorted a lot. I will try to put that coupling capacitor.

[rankot]

I put 470n cap between lug 2 of level pot and 330k resistor divider (similar to first coupling capacitor before op amp 1), and I have a nice sound now! Thanks! When I bias Q1 gate to 0.30V (trimpot measured at 3k), OS starts working, and if I bias to more (1.5V for example), I get more distortion, but that's nice distortion! So I will solder one 3k resistor befor 10k pot and use it as a distortion control.

[rankot]

Now another thing - OS sounds nice, but it kills slap tone on bass too much. Pick and fingered playing sound good. What could be the cause?

[lukeferg]

That's probably the nature of how the pedal does its compression. I think I read somewhere that the OS is more like a limiter than a comp. Thats going to cut the volume of your slaps and pops pretty sharply. I've used a multiband compressor when playing slap but I don't compress the highs at all, just the lows and mids.