GEOFEX variable stutter (cont.)

[gaussmarkov]

i am following up on this variable stutter pedal thread.  there, R.G. suggested using a particular addition to his circuit to reduce the click.  i didn't see anyone try his suggestion, so i have been doing that.  here is a link to a schematic.  here is my current draft of a breadboard layout:



i have actually only tried a previous version of this one.  i am hoping to get some help with a couple of things before doing this one.  my previous version works--in fact, i find the stutter pedal totally addictive.  the click is in my previous version and this one differs in routing the ground and 9V connections and in adding a decoupling cap (C9) to IC2's ground.

so my first question is whether this breadboard layout can be improved for removing the tick.

i have a second question/problem.  when i fired up the previous version, i toasted the 5.6V zener diode (D6).  nice little stream of smoke.  the circuit works without it so i have been playing with it without the zener.  can someone check whether i have made a mistake on that component?  R.G.'s schem does not show that diode as a zener, but he mentions that

Other JFETs work, anything with Vgsoff less than the zener voltage of 5.6V. 2SK30A works.

by the way, i am using a J201 in pleace of the 2N5485.  i have also used 1N914 diodes in place of the 1N4148 diodes specified.

thanks all, gm

[gez]

I've had a brief skim through your layout and it seems you've managed to keep ground connections for the audio and modulating circuitry separate.  However, this assumes that the board connection to your PSU/battery ground connects up in either the right hand or left hand corner, where the two ground rails are bridged.

R10 & C5 superfluous. They are there to slow down switching, which is what the trapezoid shaping circuitry is doing: R19 & C7 control the gradient of the slope so simply adjust these for a gentler incline/decline to compensate for the lack of R10 & C5.

In place of R10 & C5 I'd stick the outer lugs of a trimpot from IC3A's output to ground and its wiper would connect up via the reverse bias diode (D1) to the FET's gate.  Using a multi-turn trimmer is the best option, otherwise it can be difficult to tune, but this simple trick gets rid of a fair bit of bleedthrough.

[gaussmarkov]

hey gez!  thanks a ton for your help. 

I've had a brief skim through your layout and it seems you've managed to keep ground connections for the audio and modulating circuitry separate.  However, this assumes that the board connection to your PSU/battery ground connects up in either the right hand or left hand corner, where the two ground rails are bridged.

right.  i wasn't clear.  my intention was the upper right-hand corner.

R10 & C5 superfluous. They are there to slow down switching, which is what the trapezoid shaping circuitry is doing: R19 & C7 control the gradient of the slope so simply adjust these for a gentler incline/decline to compensate for the lack of R10 & C5.

ah ha!  makes sense.  i'm taking R10 & C5 out.  i will stick with my values on R19 & C7 for now, based on simulations.  those values and R18 are mostly guesses.  R18 is supposed to be small relative to R19, but that's all i know.

In place of R10 & C5 I'd stick the outer lugs of a trimpot from IC3A's output to ground and its wiper would connect up via the reverse bias diode (D1) to the FET's gate.  Using a multi-turn trimmer is the best option, otherwise it can be difficult to tune, but this simple trick gets rid of a fair bit of bleedthrough.

i will try this.  i also added a decoupling cap for IC3.  my simulations showed that it had the same 4mA current spike on its ground that IC2 had.  R.G. noted this phenomenon in his notes and advised the decoupling caps for his LFO opamps.  i guess the trapezoid shaping part of the circuit should be included in this version.

i have a new schem and breadboard layout based on your suggestions.  i will try the layout as soon as i can.  i don't get much time for this fun these days.    but i will keep pluggin' away as time permits.

oh, i found the reason for toasting the diode:  i had accidentally left a direct connection to +9V on another part of the board as i was rewiring.    so the diode was actually across the rails and i exceeded its power rating.  it had to be, given all that smoke.

cheers, gm

[Switch]

This sounds interesting, are there any clips of this sorta pedal in action? Can you describe it?

[gaussmarkov]

This sounds interesting, are there any clips of this sorta pedal in action? Can you describe it?

you might want to glance over previous threads that have discussed this effect.  i believe there are several descriptions.  after i reconfigure my breadboard for the latest revision, i will make a clip.

when i listen to a sustained chord or note through this it reminds me of a delay.  one of the important differences is that there is no repeat of the initial attack so it's clearly not an echo.  the note just turns back on (and off).  it's kind of robotic.  and then the natural decay of vibrating strings also seems different from the decay of a delay.

when you are picking notes along with it, you can remove the pick attack on notes that are played before the on cycle.  and when you play with the cycle out of phase with the down beat, you can get some cool rhythmic effects when notes are truncated in unusual ways.

as i said, it's addictive, like a delay can be addictive but different.

[gaussmarkov]

i've learned quite a bit from this project and i thought i would share the simulation work that i did with LTSPICE in case it helps somebody else start to use this great tool.  R.G. mentions that he simulated his circuit to check for "feed through."  though i have not figured out what he was looking for, it's still been a great exercise.  my LTSPICE file for R.G.'s variable stuttering pedal can be downloaded here.  It's an ascii file with SPICE commands.  you just need to open it up in LTSPICE and simulate>run.  just be sure to save it with a .asc extension so that it is easy to find with LTSPICE.

you will see a schematic like this when you open the file:



LTSPICE does not seem to have a pot component so i have had to replace these with a pair of resistors.  these pairs are labelled.

when you choose simulate>run from the menus, you are given a choice of what to plot.  if you choose V(out), you will get the output signal for the first 5 seconds of running the circuit.  that will look something like this:



nice stutter, eh?  this is the output for a 70mV sine wave at 1000Hz, which you can set by changing the properties of the voltage source.  if you zoom in you can see what the "on" part of the signal looks like:



if you plot the voltages within the LFO section, you can learn something about how it works.  you can find sawtooth, square, and trapezoid waves:



and you can also see the soft corners on the trapezoid shape mentioned by the author of that part of the circuit.  you can also observe the current spikes on the op amp grounds that R.G. mentions in his circuit document:



as i understand it, you need to use decoupling capacitors to guard against these causing ticks in the output signal.  and you can use this sort of simulation to choose the parts that govern the slope of the trapezoid shaper, which is also helpful for reducing tick.

enjoy, gm

[R.G.]

R.G. mentions that he simulated his circuit to check for "feed through."  though i have not figured out what he was looking for,

I was looking for output signal that was not caused by the input signal source. To do this, I set in the input signal to a few microvolts, then looked at the output signal node, and looked at the time when the LFO was turning on and off. Any transients there must be from the circuit letting part of the LFO signal through. I deemed anything over 1mV peak feedthrough as bad. That's only about -20db compared to a healthy guitar signal.

You do good work.

[gaussmarkov]

you just made my day (more like "month") -- where is the "i am thrilled" smiley?

thanks a ton, R.G. 

[gaussmarkov]

with R.G.'s explanation in hand, i ran a simulation with a 2uV input and got 5mV spikes on Vout.  then i put R.G.'s original resistor-capacitor divider in before the diode on the gate of the 2N5485.  that is, in the LTSPICE schem above, R19 became 100K and R20 became a 1nF cap.  now i am seeing 40uV peaks (near the moment where the signal gets shunted and exactly coincident with the current spikes on the ground of the trapezoid shaping op amp U5).  so that suggests keeping those in place.

one can still put gez's suggested trimmer in there in case it helps.

cheers, gm

[R.G.]

The problem with circuits like this is that the first order effects are all just fine any way you do it. But the second order effects like click feedthrough can drive you nuts, and they're very much harder to isolate and deal with.

What we are fighting in this circuit is the interelectrode capacitances in the switch JFET. The capacitances from gate to source and gate to drain - well, OK, the gate-to-channel capacitance in toto - couple any voltage changes on the gate through to the signal line.The capacitances are small, but the voltage change on the gate is big. So we have to suppress a 5V change on the gate to less than a few microvolts on the signal channel. That's a lot of isolation to do.

This circuit fights that voltage transfer two ways, by slowing down the edge change rate of the signal on the gate, and by isolating the power supplies that may couple the "tick" in through them.

But I just thought of another way. The bias resistor on the JFET drain, R5 is 1M just because I'm used to using high resistances to ensure no "on" switch losses. That could be made much lower. Change that to 100K and see what happens. It may get you a factor-of-ten improvement if that's the only place the transient comes from.

Also, you can soften the transient on ground by putting a smallish cap, maybe 10pF to 100pF across R16(150K) in the LFO. This makes the sudden reversal of direction on the Schmitt trigger less violent. I think.

[gaussmarkov]

here's what i found.  the reduction of R5 from 1M to 100K gives about 75% of the original peak, taking us from 45uV to 32uV.  a 100pF capacitor across R16 (150K) takes that down to 30uV.  10pF is not much good.

out of curiosity, i also changed C8 (the 1nF cap in your RC filter before the gate diode) to 10nF then 100nF.  that takes us down to less than 8 microvolts, with the 100K R5.  this was the schem:

[gez]

then i put R.G.'s original resistor-capacitor divider in before the diode on the gate of the 2N5485.  that is, in the LTSPICE schem above, R19 became 100K and R20 became a 1nF cap.  now i am seeing 40uV peaks (near the moment where the signal gets shunted and exactly coincident with the current spikes on the ground of the trapezoid shaping op amp U5).  so that suggests keeping those in place.

...or tweaking the trapezoid shaper, as suggested earlier.  It's there to slow down the transition from on to off, so why not use it?

As RG noted, the voltage change on the gate is big.  By dividing down this voltage using the trimmer you reduce charge injection into the gate (it's simply ohms law), in turn reducing click.  You don't need rail-to-rail swing to turn a JFET on - it's overkill really - so adding a trimmer will help a lot.

[gaussmarkov]

gez, i have experimented with changing the slope of the trapezoid shaper and i was disappointed with the results.  but that is probably because i am not the best person to exploit that idea.      the slope is already gentle, right?  if you look at the figures above, maybe 15% of the cycle is sloped.  also, i was following the advice (which i did not take the time to try to understand) of the author of the trapezoid shaping circuit to keep R17 small relative to R18.  it seemed like the direction of improvement was in the neighborhood of making these resistors close to equal.

i am sure that you are correct about the trimmer.  i was just saying that the RC filter that it replaced was helping a lot in the simulations that i was doing.  i will put it back into the simulations and check.

[gaussmarkov]

i should have thought of this without simming, i guess, but the RC filter also accomplishes what your trimmer does, right?

[gaussmarkov]

well, this is getting beyond my present analytical understanding. and some calculations would surely make more of this.  i put the trimmer between the RC filter and the trapezoid shaper and this is what i think i found.  (1) it can help just as gez says and (2) a pair of high value resistors works better than a pair of low value resistors.  a 1.1M / 1M divider got the peaks down below 5uV.

with so many component values to tweak, i'm thinking that numerical brute force or clever analytical thinking could suggest a good combination.

[gaussmarkov]

and that trimmer is affecting the duty cycle, more on than off when the duty cycle pot is at 50/50.  i also see a more pronounced effect of the the trapezoid shape: the signal is turning on and off more smoothly.

[gez]

i should have thought of this without simming, i guess, but the RC filter also accomplishes what your trimmer does, right?

Not really gm.  When you see these RC combos in switching circuits they're there to slow down the leading/falling edge of the square wave to the extent that it isn't heard (or minimised as much as possible).  The exponential ramp up/down of a cap is the easiest way to do this but creates a somewhat distorted version of a trapezoid, hence the more complicated circuitry before it.  By leaving in the RC combo you're sloping the rising/falling edges even more, and if too slow you end up with a distorted triangle wave with diminishing amplitude as frequency increases.

The pot is a no brainer.  When the gate of the FET is more positive than its source/drain, the gate-channel junction can conduct and current flows into the channel.  For this reason the reverse diode is used - it acts as a huge current limiting resistor.  You don't need the gate to be a few volts +ve of the source/drain to turn the FET on fully, so by dividing down the output of the trapezoid shaper less voltage appears across the diode.  Less voltage = less leakage current = less click.

[R.G.]

The idea voltage to be applied to the gate diode would be the bias voltage minus one diode drop plus one signal peak voltage.

The diode is acting like a switch more than a current limiter. It's there to make the gate open, which lets the channel be whatever resistance it is when the gate is not being played with.

We think of a gate as a single pin; in reality, the gate is a region of the device that overlays the channel. The gate reverse bias varies down the channel by the IR drop of the channel, which is why pinchoff occurs. The channel is more pinched off where the channel makes the gate most reverse biased. When the channel voltage is enough bigger than the gate that the variation of voltage down the channel is insignificant comparatively, the channel is fullyin pinchoff, and the current that flows is no longer resistively controlled by the drain-source voltage. The gate is in full control by how hard it pinches the channel. Hence the resistive region is small.

Getting the gate to be just open at the biggest signal is one of the better ways to turn the FET on without injecting charge. Hence the diode to prevent charge.

There are two other things that I think are going on. One is the FETs control range. Let's say that the JFET being used had a Vgsoff of 4V. So when the gate is at -4V, the channel resistance is some big resistance, but when it's only -3.9V, you can see a notable change in resistance. From there to Vgs = 0, the resistance decreases toward Rdson. To make the JFET go through this range, we need a gate signal from the source voltage down to -Vgsoff  minus a diode drop because the gate diode has to be turned on to pull the gate down.This is a good match for a 4.5-5.0V bias voltage. But if you have a lower Vgsoff JFET, then there is a portion of the turnoff voltage that is wasted because the JFET is already turned well off before the gate signal bottoms out. In fact, once the JFET is more than 10x the series resistance, you're effectively there, as from 10s the signal series resistance to infinit resistance makes little difference in the audible level of the signal. When the JFET channel resistance is 1/10 of the signal series resistance, you are already 20db down, and well into cutting off. So the range of the JFET's control voltage needed to get audible effects is even smaller. The bigger the gate signal is above this, the more excess gate signal there is to be kept out of the audio path.

I'm less sure of the second thing. I think there is an effect of the sharpness of the corners of the gate drive waveform. The intermediate slope, whether limited by a trapezoid circuit or an R-C helps with the many-volts edge of the gate drive. But I think that rounding the corners of the gate drive signal with an RC helps as well when the signal gets to the sharp corner of the gate drive. I'm still mulling this one over.

[puretube]

...about time to tame the square with a 3-legged-d*g? 

[gez]

...about time to tame the square with a 3-legged-d*g? 

Would it provide enough rounding though?  Have you tried this Ton? [/dumb question]