How does the Orange Squeezer work? Mods?

[rockgardenlove]

How does the Orange Squeezer work?
Schematic here:
http://generalguitargadgets.com/pdf/ggg_osq_sc.pdf
If somebody could explain the workings in the signal chain, that would be great.   
Also, I've got a nice box (thanks Jlullo) with two holes drilled...what's a mod that would use one more hole?  I'd add a compression pot, but I don't understand how the circuit works.
From what I understand:
The signal comes in, is boosted by the opamp.  Then the diode takes the quiet bits (forward voltage?) and sends them through the JFET to get a boost, which it then feeds back into the opamp.  What's up with the other JFET though?  I might be way off on this anyways.
Thanks!

[brett]

Hi
very briefly...
the output signal is rectified and run past a big cap (a low-pass filter).  As the voltage on the gate of the main JFET rises, it turns on and conducts signal *away* from the op-amp (thereby lowering gain).  The second JFET (with the 2.4k from gate to source) is there to help provide the right amount of bias to the main one.

There've been a few discussions of the intricacies of the OS in the past.  IIRC RG went into some detail once.
The most popular mod for most compressors would be a release control.  Replace the resistor paralllel with the cap with a pot wired as a variable resistor.
cheers

[blanik]

excuse my ignorance but what is release in a compressor? 

[brett]

Release time (or decay time, in seconds) is the time it takes for the rectified "compression" voltage to fall.
It is equal to R (in ohms) x C (in farads).
So for a given capacitor, higher resistances make the release time longer, and lower resistances make the release time shorter.
If a compressor has a short release time, the compressor may have a "wobbly" sound as the compressor turns on and off many times as a note decays. Too long is also a problem, as it doesn't allow a note to "bloom" when the compressor turns off.
cheers

[rockgardenlove]

Slowly picking through it.
So, the rectification is there to provide a charge to charge the capacitor?  What's the rectification there for?
And I'm not quite getting what's detecting when to "squeeze."  If you hit a note, it would charge up the cap.  I've got that much.  Then does the discharge of the cap allow that main JFET to operate?

[brett]

Hi

Then does the discharge of the cap allow that main JFET to operate?

You've got most of it.
Yes, the rectifier allows current to flow to the +ve of the cap and charge it (and prevents charge flowing back out).
The impedance into the JFET is millions of ohms, so the current flow out is controlled by the "release" or "bleed" resistor, as discussed above.
The JFET conducts more when the voltage difference between the gate and the source is greater.  This is known as the Vgs (voltage from gate to source).  Some JFETs have a low Vgs to turn on (e.g. less than a volt, J201s) and some have high Vgs to turn on (e.g. 3 to 5 volts, MPF102).

While the signal is large, the cap is charged, and the JFET "wastes" the signal to ground.
cheers

[R.G.]

The Technology of the Orange Squeezer
Copyright 2007 R.G. Keen

In the schematic at General Guitar Gadgets:
R1 is a pulldown resistor for minimizing switching pop.

C1 couples the signal into the device.

R2, Q2 and C3 form a voltage divider on the incoming signal. The resistance of Q2 is the lower half of the divider and C3 blocks DC. This is the gain-change heart of the unit. As Q2 is made lower resistance by letting its gate voltage get near its source voltage, its channel resistance drops to a few hundred ohms, causing the signal at its drain to become very small. As its gate is pulled to ground, lower than its source, the channel resistance becomes very large and the signal at Q2s drain is not divided down. This dividing down of the signal provides the variation in signal level in the unit, as well as the reduction of large signals to a constant level.

Q1, R5, C3, and R7 form a variable bias voltage for Q2. Q1 is used as a constant current source by placing resistor R5 from its gate to its source. This constant current causes a constant voltage across R7, depending on R7's value. R7 is variable so the bias voltage can be adjusted to match the particular device used for Q2. This adjustment is necessary because of the large variation in cutoff voltages inherent in JFETs. Q1 and Q2 do not need to be matched. They do very different jobs. R7 is there only for adjusting the source voltage of Q2 so it operates properly as detailed below.

C2, R3, and R6 form a local feedback network to linearize Q2's channel resistance. If these parts were not there, Q2 would still work, but its resistance would change with the signal level as well as the voltage on its gate-source. This is a form of distortion. These parts reduce the distortion as well as making the signal voltage range of which Q2 is capable be larger. 

IC1, R4, R8, R9, R10, C5, C6, and R13 form a gain block which amplifies the signal by a fixed amount of 1+(220K/10K) = 23 times after it goes through the input signal divider. This gain provides the extra signal level to bring up small signals to a constant level.

R11, D1, R12, and C7 form an envelope detector. D1 rectifies positive signal peaks and charges C7 up to a voltage slightly less than the peak of the output signal at the output of the gain stage. The current into C7 is limited by R11, which limits how fast C7 can charge. R11 then controls the attack time of the compressor. R12 leaks charge out of C7 and so controls the release time. When the voltage on C7 is high, it is near the voltage provided to Q2's gate across R7. This makes Q2's channel resistance small and divides the incoming signal down. When the voltage on C7 is small, the voltage at Q2's gate is much lower than its source, making its channel resistance high and not dividing down the input signal so much.

The forward turn-on voltage of D1 is subtracted from the signal peak, and so is an error term in detecting the envelope of the signal. This is why D1 is specified as 1N100, a germanium device.

The overall operation is that with no signal, the voltage at C7 is pulled to ground by R12, so Q2 is off and the incoming signal is not divided down. Noise and hum below the threshold of D1's forward voltage are still amplified, so it is noisy when there is no signal, like all compressors. When a signal comes in, the first signal peak to exceed D1's forward voltage charges C7, which increases Q2's gate voltage, making Vgs on Q2 smaller and lowering its channel resistance. The next peaks may or may not be large enough to charge C7. If they're larger, C7's voltage increases and the signal is divided down more. If they're smaller, voltage leaks out through R12 until there is just enough charge coming in through D1 to balance charge leaking out through R12. R7 should be adjusted by ear to provide the most compression range at the output with minimal distortion.

This is a feedback style compressor. The signal level is sensed at the output of the compressor, manipulated in some circuitry and made to decrease the signal level coming through the compressor. Feedback style compressors tend to provide an almost constant output level when the signal level is inside their active range. Feed-forward compressors sense signal level at the input and send a signal that reduces/increases gain in stages after the input. Feed-forward compressors have a kind of looser grip on signal level, and tend to have output signals that vary more than feed-back compressors, but sound more natural. Guitarists like feed-back compressors, vocalists and studios like feed-forward compressors.

All rights reserved. Posted to diystompboxes.com by permission.
No permission for reposting to other web pages or any other use.

[wampcat1]

The Technology of the Orange Squeezer
Copyright 2007 R.G. Keen

In the schematic at General Guitar Gadgets:
R1 is a pulldown resistor for minimizing switching pop.

C1 couples the signal into the device.

R2, Q2 and C3 form a voltage divider on the incoming signal. The resistance of Q2 is the lower half of the divider and C3 blocks DC. This is the gain-change heart of the unit. As Q2 is made lower resistance by letting its gate voltage get near its source voltage, its channel resistance drops to a few hundred ohms, causing the signal at its drain to become very small. As its gate is pulled to ground, lower than its source, the channel resistance becomes very large and the signal at Q2s drain is not divided down. This dividing down of the signal provides the variation in signal level in the unit, as well as the reduction of large signals to a constant level.

Q1, R5, C3, and R7 form a variable bias voltage for Q2. Q1 is used as a constant current source by placing resistor R5 from its gate to its source. This constant current causes a constant voltage across R7, depending on R7's value. R7 is variable so the bias voltage can be adjusted to match the particular device used for Q2. This adjustment is necessary because of the large variation in cutoff voltages inherent in JFETs. Q1 and Q2 do not need to be matched. They do very different jobs. R7 is there only for adjusting the source voltage of Q2 so it operates properly as detailed below.

C2, R3, and R6 form a local feedback network to linearize Q2's channel resistance. If these parts were not there, Q2 would still work, but its resistance would change with the signal level as well as the voltage on its gate-source. This is a form of distortion. These parts reduce the distortion as well as making the signal voltage range of which Q2 is capable be larger. 

IC1, R4, R8, R9, R10, C5, C6, and R13 form a gain block which amplifies the signal by a fixed amount of 1+(220K/10K) = 23 times after it goes through the input signal divider. This gain provides the extra signal level to bring up small signals to a constant level.

R11, D1, R12, and C7 form an envelope detector. D1 rectifies positive signal peaks and charges C7 up to a voltage slightly less than the peak of the output signal at the output of the gain stage. The current into C7 is limited by R11, which limits how fast C7 can charge. R11 then controls the attack time of the compressor. R12 leaks charge out of C7 and so controls the release time. When the voltage on C7 is high, it is near the voltage provided to Q2's gate across R7. This makes Q2's channel resistance small and divides the incoming signal down. When the voltage on C7 is small, the voltage at Q2's gate is much lower than its source, making its channel resistance high and not dividing down the input signal so much.

The forward turn-on voltage of D1 is subtracted from the signal peak, and so is an error term in detecting the envelope of the signal. This is why D1 is specified as 1N100, a germanium device.

The overall operation is that with no signal, the voltage at C7 is pulled to ground by R12, so Q2 is off and the incoming signal is not divided down. Noise and hum below the threshold of D1's forward voltage are still amplified, so it is noisy when there is no signal, like all compressors. When a signal comes in, the first signal peak to exceed D1's forward voltage charges C7, which increases Q2's gate voltage, making Vgs on Q2 smaller and lowering its channel resistance. The next peaks may or may not be large enough to charge C7. If they're larger, C7's voltage increases and the signal is divided down more. If they're smaller, voltage leaks out through R12 until there is just enough charge coming in through D1 to balance charge leaking out through R12. R7 should be adjusted by ear to provide the most compression range at the output with minimal distortion.

This is a feedback style compressor. The signal level is sensed at the output of the compressor, manipulated in some circuitry and made to decrease the signal level coming through the compressor. Feedback style compressors tend to provide an almost constant output level when the signal level is inside their active range. Feed-forward compressors sense signal level at the input and send a signal that reduces/increases gain in stages after the input. Feed-forward compressors have a kind of looser grip on signal level, and tend to have output signals that vary more than feed-back compressors, but sound more natural. Guitarists like feed-back compressors, vocalists and studios like feed-forward compressors.

All rights reserved. Posted to diystompboxes.com by permission.
No permission for reposting to other web pages or any other use.

that's a goody!! somebody post that to wiki!

[markm]

Very Cool indeed R.G.
Thanks VERY much! 

[Meanderthal]

 javascript:void(0);
Shockedjavascript:void(0);
icon_cooljavascript:void(0);
Grin

Errr... well, cool! that answered every question I would ever have had!

[R.G.]

that's a goody!! somebody post that to wiki!

Actually, don't.

It won't be here long, as it's going into the "Technology of... " series at GEO, at which point permission for posting here will be invalidated.

Sorry - but at GEO I can update it with more to-the-point schematic fragments and other artwork.

[markm]

R.G.,
Please let us know when you get the O/S info posted on your site, the completed article would make some interesting and informative reading.
Thanks again Sir! 

[rockgardenlove]

So I'm looking through it, and it all makes sense to me, in rough terms at least, until it comes to the working of the JFETS.  I'm familiar with them set up in the typical gain stage setup, but I don't really understand how they're working in these conditions.
A larger voltage on the gait would open up the connection between the input and C3 bleeding it off to ground?  Is that right?
And why is the 2200pF and 470KΩ right there?  It can't be for biasing (I don't think) as the cap would block any DC.  Hmm?

Thanks guys!   
This place rules.

[dachshund]

If I'm reading correctly, there is a pot on the schematic, a 10K at R7.
This is the pot to bring out to the chassis?
Also, is the 10K volume pot linear?
thanks.

[rockgardenlove]

The pot to bring to the chassis is the one at the far right hand of the circuit.  And it should be audio taper for a smoother (in volume) sweep.

[R.G.]

So I'm looking through it, and it all makes sense to me, in rough terms at least, until it comes to the working of the JFETS.  I'm familiar with them set up in the typical gain stage setup, but I don't really understand how they're working in these conditions.

All JFETs are voltage controlled resistors. The channel of the JFET is a single doped silicon resistor. The gate is an oppositely doped layer on top. When the gate is made more negative than the channel, it pulls the channel charge carriers to it and narrows the region of the channel that can carry charge. Just like a garden hose, the gate literally pinches off the flow of current through the channel. For the region where the voltage across drain and source is low, the resistor looks just like a variable resistor. That's how Q2 is working - a voltage variable resistor.

When the voltage across drain and source is larger, the channel gets "pinched off" and large increases in voltage can't increase the current flow in the channel. The drain/source channel becomes a voltage controlled current limiter. Q1 is working this way. The source resistor on Q1 is setting the current by setting a certain amount of negative voltage for the gate by the source current flow.

A larger voltage on the gait would open up the connection between the input and C3 bleeding it off to ground?  Is that right?

On Q2, a voltage which is higher - that is, closer to the voltage where the source is being held by the voltage on R7 - makes the Q2 channel less constricted, so it acts like a lower resistance and shunts more signal to ground through C3. "Bleeding off" is not really accurate. R2 and Q2 form an AC-only voltage divider. C3 lets it float up for DC but still be AC-grounded.

And why is the 2200pF and 470KΩ right there?  It can't be for biasing (I don't think) as the cap would block any DC.  Hmm?

Quoting from "The Technology of the Orange Squeezer",

C2, R3, and R6 form a local feedback network to linearize Q2's channel resistance. If these parts were not there, Q2 would still work, but its resistance would change with the signal level as well as the voltage on its gate-source. This is a form of distortion. These parts reduce the distortion as well as making the signal voltage range of which Q2 is capable be larger.

It allows bigger input signals and wider compression range without noticeable distortion.

[rockgardenlove]

So I'm looking through it, and it all makes sense to me, in rough terms at least, until it comes to the working of the JFETS.  I'm familiar with them set up in the typical gain stage setup, but I don't really understand how they're working in these conditions.

All JFETs are voltage controlled resistors. The channel of the JFET is a single doped silicon resistor. The gate is an oppositely doped layer on top. When the gate is made more negative than the channel, it pulls the channel charge carriers to it and narrows the region of the channel that can carry charge. Just like a garden hose, the gate literally pinches off the flow of current through the channel. For the region where the voltage across drain and source is low, the resistor looks just like a variable resistor. That's how Q2 is working - a voltage variable resistor.

When the voltage across drain and source is larger, the channel gets "pinched off" and large increases in voltage can't increase the current flow in the channel. The drain/source channel becomes a voltage controlled current limiter. Q1 is working this way. The source resistor on Q1 is setting the current by setting a certain amount of negative voltage for the gate by the source current flow.

Wait, do you mean gate and source?

A larger voltage on the gait would open up the connection between the input and C3 bleeding it off to ground?  Is that right?

On Q2, a voltage which is higher - that is, closer to the voltage where the source is being held by the voltage on R7 - makes the Q2 channel less constricted, so it acts like a lower resistance and shunts more signal to ground through C3. "Bleeding off" is not really accurate. R2 and Q2 form an AC-only voltage divider. C3 lets it float up for DC but still be AC-grounded.

And why is the 2200pF and 470KΩ right there?  It can't be for biasing (I don't think) as the cap would block any DC.  Hmm?

Quoting from "The Technology of the Orange Squeezer",

C2, R3, and R6 form a local feedback network to linearize Q2's channel resistance. If these parts were not there, Q2 would still work, but its resistance would change with the signal level as well as the voltage on its gate-source. This is a form of distortion. These parts reduce the distortion as well as making the signal voltage range of which Q2 is capable be larger.

It allows bigger input signals and wider compression range without noticeable distortion.

[R.G.]

Wait, do you mean gate and source?

No, I mean drain and source.

The channel has length. Since it is a resistor, it drops voltage down the length of it as current flows through it. Since the gate has no current flowing into or out of it, every point on the gate is at the same voltage. That means that the voltage between the gate and channel is more negative at the drain end than at the source end, so there is a range of pinch-offed-ness down the length of the channel.

For low currents, this difference in pinched-ness from drain to source is trivial and can be ignored. In those low current, low voltage regions of operation, the channel looks like a linear and variable resistor. When the current through the channel becomes big enough that the voltage variation down the length of the channel can't be ignored any more, you enter the ... ta-da... pinch off region. Here, the channel is pinched down to a threadlike area of conduction. It can't pinch off completely on its own because that would stop the current flow that's pinching it off, but what it does is pinch down to a constant current flow. In the pinchoff region, JFETs look like constant current sources, the current being controlled by Vgs.

What's confusing you is that the JFET changes hats. For low voltages and currents, in the so-called triode region, JFETs really, truly are voltage variable resistors. At bigger channel currents and voltages, they change over to looking like constant current sources. That and I tried to get people to leap over the difference between triode region and pinchoff region without a full explanation... 

[rockgardenlove]

Wait, do you mean gate and source?

No, I mean drain and source.

The channel has length. Since it is a resistor, it drops voltage down the length of it as current flows through it. Since the gate has no current flowing into or out of it, every point on the gate is at the same voltage. That means that the voltage between the gate and channel is more negative at the drain end than at the source end, so there is a range of pinch-offed-ness down the length of the channel.

How is the drain end more negative than the source end, when the source is hooked down into ground and the drain isn't?
Or is this where Q1 comes into play...the voltage from Q1's drain goes through it as a resistor, then through r5 and up to the source, making it more positive(because of C3 and R7).

For low currents, this difference in pinched-ness from drain to source is trivial and can be ignored. In those low current, low voltage regions of operation, the channel looks like a linear and variable resistor. When the current through the channel becomes big enough that the voltage variation down the length of the channel can't be ignored any more, you enter the ... ta-da... pinch off region. Here, the channel is pinched down to a threadlike area of conduction. It can't pinch off completely on its own because that would stop the current flow that's pinching it off, but what it does is pinch down to a constant current flow. In the pinchoff region, JFETs look like constant current sources, the current being controlled by Vgs.

I think this is starting to make sense.  (Well, to me at least...as to my thoughts being right, who knows?  )  As the "tension" (not very good with describing what's going on in my head...does this make sense?) from the source-drain is what's pinching it, it can't go too low or else the pinch is gone.
So the discharge from that cap changes the "Vgs" and therefore varies the degree of pinch?

[R.G.]

How is the drain end more negative than the source end, when the source is hooked down into ground and the drain isn't?

Watch carefully.

The channel is a resistor, with drain on the high voltage end and source on the low voltage end.
When current flows in the channel, the voltage at the drain end is higher than the voltage at the source end.
The gate is a blanket - it overlays the entire channel.
The gate has no current flowing through it, so the voltage on the gate is constant all over the gate.
The source is held at some voltage. Let's call this Vbias. It's set by Q1 letting a constant current flow through R7, but it might as well be a battery. It doesn't change while the pedal is operating.
So the gate has two ends - the drain end and the source end. These are at the exact same voltage.

If the gate is held at a voltage Vgate, and this voltage is less than the source voltage (Vbias), then the voltage on the gate is the difference between Vbias and Vgate. We deliberately make Vgate lower than Vsource to reverse bias the gate.

But the gate region overlays the entire channel, not just the source. The source end is indeed at Vbias-Vgate. But since the drain end of the channel is at a higher voltage because current is flowing through it, the microscopic portion of the gate overlaying the channel at the drain end sees not only the gate-to-source voltage, but also the additional voltage of the resistive drop of the channel due to any current flowing through it.

For example: assume that we have a JFET where we have tied the source to 3Vdc and the gate to 1Vdc. The gate to source voltage is then -2V because the gate is less positive than the source. The gate is relatively more negative than the source.

Further assume that this particular JFET has a drain-source resistance of 10K ohms at Vgs=-2V. If we hook up a power supply to the drain, then current flows through the 10K drain-to-source resistance. Let's imagine that the power supply externals are set up so that 100uA flows through the channel. The channel then has a voltage drop of V = 100uA*10K = 1V.

So the drain end of the JFET is 1V more positive than the source end. It's at +4V, not +3V like the source end. That means that the channel is more choked off at the drain end than the source end because of the current flowing through the channel.

So the gate, which has the same voltage all over, is more negative with respect to the channel at the drain end than it is at the source end. It's the relative voltage between the gate and channel right under it that determines what happens. It's not the drain that's more negative, it's the gate relative to the drain.

And since the gate overlays the whole channel, the drain end of the gate has a bias on it of -3V. The source end of the gate has a voltage on it of -2V.