Jfet matching for phase 45 IC question

[killerkev]

Hello, I'm trying to match Jfets for a phase 45. I made up a GeoFEx.com "Improved fet matcher" but I only have a TL072 IC that the build calls for to put in the "Matcher" but Geofex calls for a TL071. I checked out the data sheet of the Fairchild TL072 & TL071 (http://focus.ti.com/lit/ds/symlink/tl071a.pdf) and adjusted for Vcc+ & OUT (pin 6 & 7 on the 071 to pin 7 & 8 on the 072) but I get the same readings for every J201 when in or not. Can I use this IC and need additional adjustments or do I need a TL071? Help please!

[R.G.]

The TL072 is two 071's in the same package. You must adjust EVERY pin you use to match the new package.

Pin 8 must be +V. P4 must be ground. You must use EITHER pins 1,2,3 or pins 5,6, and 7 for the opamp output, - input, and +input. Once you do that, it should work fine.

[niggez]

And if you dont get it working, the jfets can be matched fairly well by ear in the phase 45. Thats what i did, because i couldnt get the matcher to work. So in case you dont get it working, simply socket your fets one at a time (with one fet inserted, the phasing is not as strong, but you can hear it well), and turn the trimpot. Note the "sweet" spot and select 2 that are close together, and there you go.

[mac]

If you want you can measure Vgs at different values of Rset (IIRC RG schem) to ensure matching across the whole range, say 1k to 10k, athough it is not a must.
I did it for my P90 because I have a lot of free time

mac

[killerkev]

Thanks for replying R.G.
I understand what your saying about it being two TL071 in one package. So what I did was adjust everything to feed the 2nd stage. It didn't seem to work so I then switched it to feed the 1st stage...still didn't work so I'm gonna tell ya everything I did and maybe you can tell me where I'm off. I'm sticking with using the 1st stage of the TL072. I made a board according to this layout:

http://i91.photobucket.com/albums/k301/killerkev_01/Jfet_Matcher_6.gif

R1-3 are 10K, and C1 is a 10uf electro. Pin 2 on a TL071 is the IN-, this is the same pin on the 072. This is also connected to the Drain & R2 which goes to ground (neg battery connection). IN+ goes to pin 3 which again is the same on both IC's. This goes to R3 and the neg. DMM connection. Pin 8 is Vcc+ which is connected to the positive power source from the battery & the Source of the Jfet and R1 (TL071 has Vcc+ as pin 7). Vcc- on TL072 is the same on both, pin 4 which goes directy to ground (neg. connection of battery).  LAst but not least, pin 1 on TL072 is the OUT for the 1st stage (which was pin 6 on the TL071) which is connected to the Gate of the FET and the + DMM connection.

So there it is. Any help from anyone is greatly appreciated! Maybe something is screwed up... I'm not sure since this is my first time working with FETs and IC's.  When everything is connected except for the Fet, I'm getting around +3.8v.  Once I put a Fairchild J201 Fet in, I get around -0.08V for all Fet's. I have 25 of these to check out to make my phase 45..... Was maybe looking into the future for a phase 90 but things haven't been going well as all can see.

[killerkev]

 ;DBUMP

[dxm1]

LAst but not least, pin 1 on TL072 is the OUT for the 1st stage (which was pin 6 on the TL071) which is connected to the Gate of the FET and the + DMM connection.

Check the layout again - you are taking the output from pin 6, instead of pin one.

[killerkev]

The layout for the TL072 shows pin 6 as 2IN-. The layout shows pin 1 as the 1OUT.

[killerkev]

I'm refering to the datasheet of the IC's in the first post, not the layout of the matcher.

[R.G.]

Your layout has a couple of flaws in it.

First: you're misunderstanding how pinouts from datasheets work, I think. Pins 1, 2, and 3 are for opamp 1, pins 5,6,& 7 are for opamp 2. Your layout still uses pins 2, 3, and 6.
Second, you have pin 7 connected to the positive power supply, which is correct for a single, but not for a dual.
Third, you have the connections to the JFET labeled incorrectly.

Here's how to correct your layout:
1. Move the connection to +9V to pin 8
2. Move the connection to the JFET gate and DMM to pin 1.
3. The drain must contact +9V and the source pin 2 for N-channel JFETs. Many of these are symmetrical so the drain and source are interchangeable, but some are not, so you might as well get the labeling right.

I believe it will work much better this way.

[killerkev]

Humm, that's interesting! I guess using a dual channel TL072 requires some modification in order to use the "JFET Matcher". Let me say that the layout for the "Jfet Matcher" is not mine. I know little about IC's.....I understand that pins 1, 2, & 3 are for opamp 1 and 5, 6, 7 are for opamp 2. I've attempted to modify the pinouts of the "Matcher" to fit my TL 072.  Here are my interpertation of your remarks:

1. +9V to pin 8: got it, it's been there.  This powers both channels of the TL 072.
2.  Move the connection to the JFET gate and DMM to pin 1: This also was done
3. The drain must contact +9V and the source pin 2 for N-channel JFETs. Many of these are symmetrical so the drain and source are interchangeable, but some are not, so you might as well get the labeling right.

3.  I'll have to connect the drain to the +9v and pin 2 (1 IN-) to +9v. This is not the way it is layed out on the "Matcher" but what do I know.  I don't understand what you mean in the second sentence. Both the Drain and Source require +9V in a TL 072?

[dxm1]

Maybe this will help?

[killerkev]

Wow! Awesome David. I'll try it out and cross my fingers! Thanks much!

[killerkev]

Well, it didn't work. I re-assembled according to dxm1 layout but nothing.  R.G. mentioned that pin 2 needed to contact +9v and Drain and words about symmetry exchanging Drain & Source which I don't understand. I think I'll try to reconfigure the layout to what R.G. is saying  & review his improved JFET matcher.