[ ? ] Continuously variable phase LFO?

[Eb7+9]

Beyond that, a PLL is a feedback system. The error in a PLL is analogous to the error in an opamp or other feedback system. ... The point of that is that the loop gain drives the sensed phase error toward zero.

if NFB nulled out offsets in gainy loop systems (why they're always input referred) there wouldn't be offset issues in opamp circuits, but there are - NFB doesn't null those out ... likewise NFB in a Phase-Locked loop won't do the same - otherwsie all PLL designs would exhibit by default maximum BERs (bit-error rates) by design as you describe it ...

in Data Recovery terms the "center of the eye" performance (zero offset target) provides a measure of immunity against jitter in the data extraction sense - that part we're not interested in here ... tough, the low-jitter goal is applicable enough for the sake of producing a stable (tracking) sine wave ... so we can use the basic idea of a zero offset tracking circuit and its low output jitter nature in this "still unseen application" situation ... btw, this architecture is also known for cleaning up jitter (clock conditioning) in timing repeaters ...

Though here we have it especially easy, with a steady stream of zeros and ones (a data signal acting like a clock) following the sine-to-square comparators ... it's easier for a clock extracting PLL to lock onto a constant series of 0/1's than a pseudo random data stream - in the process yielding minimum possible output jitter on the recovery LFO ... so piece of cake in principle for this typical Data Recovery architecture ... then it's just a matter of controlling the phase-offset component when in lock ...

So I fired up the circuit simulator and started prototyping PLLs. Had a fun couple of hours.    What I found was that nothing I could simulate would give me a stable, useful phase offset; this included multiplier, XOR, and latched phase detectors ...

doubtful ... sorry, but unless you've discovered something the entire Data Recovery industry doesn't know mixed-mode Spice sims for complete PLLs typically takes days (at best) or weeks to run and show lock, even in simple circuits - of course that's unless you're allowing gross modeling inaccuracies ... also, not to sound pedagogical or anything, you don't run to the simulator to learn basic theory, it's there to confirm the thinking ...

It is entirely possible that there is something hidden there that I don't know. So let's do this JC - post a source for the info on a variable Hogge detector output, as I have. I'm sure you must have done your research before posting, as I did.  You may also want to post your proposed circuit in the interest of being clear.

google Clock Recovery PLL and you'll find that the Hogge and Alexandere Phase Detectors are the darlings of the industry ... in your searches keep an eye open for a delay block (two inverters with a cap between them) that is typically inserted in the Hogge detector to cancel out a propagation delay borne offset current in the charge pump - though this is useful only in very high speed circuits it's telling us something right off the bat about offset existence/reduction ... in either case it's easier to correct (or alternately, intentionally insert) an offset component either as a mismatch in the current pump or as an equivalent DC current into the averaging cap

Basic theory of operation says that the loop using a Hogge detector will stabilize when the up/dn currents are the same going into the cap - this can ALSO occur if the signals are out-of-phase and the current-pump has a proportional offset equal (in charge envelope per cycle) to the phase offset times - one skewing is canceled by the other through NFB which results in a stable phase offset taking place when in lock ... btw, the math for this PLL design falls inside the basic linear-phase theory - Hogge is a linear-phase detector with it's PD gain curve equal in slope in both directions ...

I once talked about using a modern development of this kind of architecture, augmented with an adaptive filter switch (set by a cycle-slip detector), which allows faster locking of notes in a synthesizer guitar tracker circuit ... but as I recall that hit a nerve or something ...

before I reveal my measly opto-converter block to the whirl I'd like to see what we're applying this idea to first ...

[gez]

before I reveal my measly opto-converter block to the whirl I'd like to see what we're applying this idea to first ...

Reply 28, Page 2

[slacker]

I tried to make something out of that one, as the Johnson counter sine wave converter is a favorite of mine. I think it will be severely limited in the amount of phase shift, because each of the output square waves is offset by no more than one period of the square waves.

Yeah you're right, I did have my doubts about it working because it seemed too simple but I couldn't put my finger on what it was.

[R.G.]

Beyond that, a PLL is a feedback system. The error in a PLL is analogous to the error in an opamp or other feedback system. ... The point of that is that the loop gain drives the sensed phase error toward zero.

if NFB nulled out offsets in gainy loop systems (why they're always input referred) there wouldn't be offset issues in opamp circuits, but there are - NFB doesn't null those out ... likewise NFB in a Phase-Locked loop won't do the same - otherwsie all PLL designs would exhibit by default maximum BERs (bit-error rates) by design as you describe it ...

There are several reasons behind that not following. First of all, I was referring to loop error, not offset error. A feedback system must have some error at its inputs to sustain a non-zero output. It is the error that drives the forward gain of the system to move the output. An otherwise theoretically perfect opamp with less than infinite open loop gain would still have a nonzero error at its inputs in operation. This error residue is that provides the input signal to the amplifier inside the loop to move away from rest.

Offset error is another thing entirely; I believe you may be confusing terms. In opamps, offset error is an inherent mismatch which makes the amplifier be balanced when the two inputs are not at exactly equal voltages, but rather at some slightly different voltage. The usual source of the error is mismatched input devices, but there can be internal issues as well. In any case this offset causes a static offset at the output. As an example, an opamp with an input offset error of 10mV is balanced when the inputs are 10mV apart, not 0V apart. As a result, the feedback loop causes the output to be off by the closed loop gain times the input offset. A gain-of-ten amp with a 10mV input offset will have an output offset at balance of 100mV.

That says nothing at all about the error signal, often called residue or error residue caused by the finite forward gain in the loop at all. Back at PLLs, yes they follow this kind of beginner's basic control theory too. They can have input offset errors or the equivalent; these are uglinesses that good designers try to minimize. There are also error residues; in feedback systems with less than infinite gain, these are what drive the system to non zero output, and as such are always there. I can refer you to a good beginner's text on control theory if you'd like to read up on this.

in Data Recovery terms the "center of the eye" performance (zero offset target) provides a measure of immunity against jitter in the data extraction sense - that part we're not interested in here ... tough, the low-jitter goal is applicable enough for the sake of producing a stable (tracking) sine wave ... so we can use the basic idea of a zero offset tracking circuit and its low output jitter nature in this "still unseen application" situation ... btw, this architecture is also known for cleaning up jitter (clock conditioning) in timing repeaters ...

Phase jitter in PLL systems is an imperfection of another nature. It's mainly a consequence of the imperfections of the phase detector in spotting edges (which in digital systems serve as the reference for "in phase"). And I'm not sure why you're trying to deal with "that part we're not interested in here".

Though here we have it especially easy, with a steady stream of zeros and ones (a data signal acting like a clock) following the sine-to-square comparators ... it's easier for a clock extracting PLL to lock onto a constant series of 0/1's than a pseudo random data stream - in the process yielding minimum possible output jitter on the recovery LFO ... so piece of cake in principle for this typical Data Recovery architecture ... then it's just a matter of controlling the phase-offset component when in lock ...

I think you may have some confusion going on there. I'm with you on this assertion right down to "then it's just a matter".  The problem is that I can find only the one patent from 2006 that offers some scheme for doing this. In fact, all the literature I can find supports my memory in phase detectors driving phase offset to fixed positions, not variable ones.

It's kind of like we already know of an interstellar warp drive - the Alcubierre metric solutions to general relativity (http://en.wikipedia.org/wiki/Alcubierre_drive) describe a "warp bubble" that moves through space at speeds faster than light and carriers the contents of the bubble along with no FTL violations inside the bubble. Then it's "just a matter" of making these bubbles, right? It seems that estimates of the energy needed to make one range between the complete conversion to energy of several solar masses at the low end and tens of times the entire mass of the universe on the other end. That "only a matter" business is important. 

So I fired up the circuit simulator and started prototyping PLLs. Had a fun couple of hours.    What I found was that nothing I could simulate would give me a stable, useful phase offset; this included multiplier, XOR, and latched phase detectors ...

doubtful ... sorry, but unless you've discovered something the entire Data Recovery industry doesn't know mixed-mode Spice sims for complete PLLs typically takes days (at best) or weeks to run and show lock, even in simple circuits - of course that's unless you're allowing gross modeling inaccuracies ... also, not to sound pedagogical or anything, you don't run to the simulator to learn basic theory, it's there to confirm the thinking ...

Yeah, that's kinda what I was doing, using the simulator to confirm the thinking. Did you really think that I don't know about the issues in simulators? Come on JC, get serious. You're not sounding pedagogical, you're grasping at straws.

It is entirely possible that there is something hidden there that I don't know. So let's do this JC - post a source for the info on a variable Hogge detector output, as I have. I'm sure you must have done your research before posting, as I did.  You may also want to post your proposed circuit in the interest of being clear.

google Clock Recovery PLL and you'll find that the Hogge and Alexandere Phase Detectors are the darlings of the industry ... in your searches keep an eye open for a delay block (two inverters with a cap between them) that is typically inserted in the Hogge detector to cancel out a propagation delay borne offset current in the charge pump - though this is useful only in very high speed circuits it's telling us something right off the bat about offset existence/reduction ... in either case it's easier to correct (or alternately, intentionally insert) an offset component either as a mismatch in the current pump or as an equivalent DC current into the averaging cap

Actually, I meant the variable Hogge detector. And oddly enough, I did google plls of all kinds, both eyes open. The info I found indicated that there was some limited offset correction, of the order of phase jitter. This is by no means a 0-360 phase shift by twiddling a knob. What I found was telling us that there is some small offset correction.

Basic theory of operation says that the loop using a Hogge detector will stabilize when the up/dn currents are the same going into the cap - this can ALSO occur if the signals are out-of-phase and the current-pump has a proportional offset equal (in charge envelope per cycle) to the phase offset times - one skewing is canceled by the other through NFB which results in a stable phase offset taking place when in lock ... btw, the math for this PLL design falls inside the basic linear-phase theory - Hogge is a linear-phase detector with it's PD gain curve equal in slope in both directions ...

Yes, that is what the basic theory says. However, unless I miss some issues, this does not change the eventual outcome outside the PD in the VCO. As I said, I'm willing to learn - point me to it. 

I once talked about using a modern development of this kind of architecture, augmented with an adaptive filter switch (set by a cycle-slip detector), which allows faster locking of notes in a synthesizer guitar tracker circuit ... but as I recall that hit a nerve or something ...

Wow that would be really cool. Got a circuit which demonstrates that? That needs less than three solar masses of energy?

before I reveal my measly opto-converter block to the whirl I'd like to see what we're applying this idea to first ...

I think if I were in your position I would too.

[puretube]

...
The simple and straightforward version as shown has all the gain lumped at one place in the chain. That means that the loss in signal is distributed in each stage. The 45-er would be perfect if you could get the gain *and* lossed distributed into each stage. That would keep all the waveforms the same size and make it easier to do the kinds of mixing needed for variable phase results. The all-opamps version does this by making all the losses just about nil. Another way, even simpler, is to use the 45er as is, but put a resistor divider on each stage to make the higher-output stages be the same as the lowest output stage. Probably work just as well.

Note however, that unlike the more "usual"  3stage hi-pass or lo-pass phaseshiftoscillators, which need a gain of ~27 in the loop
(can`t remember the gain needed for 4 stages...),
the "45er`s" loop gain is merely slightly higher than 2  .
(even less in a theoretical perfect (simulated) circuit... give spice a few seconds to get the wave started...  )

BTW.: in the other "usual" 3- or 4-stage phaseshiftoscillators and phaseshifters per se,
I prefer the lo-pass configuration because of its inherit smoothing capability in combination with AGC,
noise rejection, and forgivingness cc. being overdriven at its hottests spots...
(if it weren`t for the neccessity of floating (series-) variable resistors...  )

[R.G.]

Note however, that unlike the more "usual"  3stage hi-pass or lo-pass phaseshiftoscillators, which need a gain of ~27 in the loop
(can`t remember the gain needed for 4 stages...), the "45er`s" loop gain is merely slightly higher than 2 

Yes, that's par for circuits which buffer between the RC phase shift stages. I remember seeing a circuit in one of TI's analog app notes using four opamp buffered RC stages and the necessary gain was microscopic.

It seems that each stage is operating at a "gain" of about one over the fourth root of two, about  0.84.

BTW.: in the other "usual" 3- or 4-stage phaseshiftoscillators and phaseshifters per se,
I prefer the lo-pass configuration because of its inherit smoothing capability in combination with AGC,
noise rejection, and forgivingness cc. being overdriven at its hottests spots...
(if it weren`t for the neccessity of floating (series-) variable resistors... 

Yep that is nice.

[puretube]

How about starting Charlies new "Sway-LFO" with a simple 2-stage design using 2 identical caps and 2 voltage-controllable resistors,
that offers both: a triangular wave, and a sinewave output?
Fixed 90 degrees apart?




(as a regular 1 pot basic LFO, and later add  the "back-and-forth" feature)?



movieclip...

[R.G.]

If you're going to use an LM13700, why not either use the two halves as a double integrator quadrature generator, or use them as a state variable band- or low-pass filter and a Schmitt trigger to make a square wave so you could do a square -> sine filter generator?

[puretube]

If you're going to use an LM13700, why not either use the two halves as a double integrator quadrature generator, or use them as a state variable band- or low-pass filter and a Schmitt trigger to make a square wave so you could do a square -> sine filter generator?

I prefer the option of switching from TRI to SINE for the 2nd (90°) output,
and also don`t want choppy slopes (click...)


(switched to sine-sine)

( clip )


Ooops, the schemo was missing... 

[gez]

Ton, how come you get a triangle wavefrom from one of the outputs?  I'd have thought both outputs would have been sine.  Is it something to do with feedback from that 100k trim in parallel with the back-to-back diodes?? 

[puretube]

simplified version:



@ C1 = C2 = 100n, f = 0.2Hz ... 200Hz

[puretube]

Ton, how come you get a triangle wavefrom from one of the outputs?  I'd have thought both outputs would have been sine.  Is it something to do with feedback from that 100k trim in parallel with the back-to-back diodes?? 

`t happened by accident on the breadboard...  , but I declare it a "feature", now. 
see in the simplified version:

http://img.photobucket.com/albums/v442/lectronix/2008_dec/simpquad-1k.jpg

in IC-B, the inv. input goes to half supply directly now,
while the 1 leftover 1k either is connected to the noninverting input for SINE,
or disconnected for TRI @ the phi-2 output...
(while output phi-1 remains sine...)

(the TRI has a larger amplitude, though (4V), than the SINE (3V)) - the scope-pic in reply#66 was with attenuated tri...
in reality it looks like this:
TRISINE_90 clip

In the original schemo, that`s why there is an
asterisk at the upper 1k of IC-B:
either have it as is in the schem for SINE,
or disconnect the righthandside of the resistor (at: "x") from pin 14, and hook it to pin 13 (at: "y") for TRI instead!

A funny gag for folx who don`t care about waveforms... 

In "SINE-SINE_90" mode, the amplitudes are equal, and sway around Ub/2 symmetrically.

The TRIMpot in the original schemo allows for dialing in a compromise between maximum achievable amplitude,
and minimum possible distortion. (best between 2Vpp and 4Vpp). - for folx with scope...

[gez]

Thanks Ton, I think I've got it.  With one switch position the previous stage isn't divided down, so with max amplitude signal it's almost like driving an integrator with a square...hence triangle?

I think the quad triangle oscillator I posted could have a decent phase shift with the addition of a PLL.  Use a variable threshold for the comparator to achieve 180 degree phase shift, then follow with a 4046 to correct the waveform to 50:50 duty cycle.  The squared signal then drives the remainder of the circuit (the second integrator).  An extra chip and only a few more components.

[puretube]

Seeing reply#8,
I hooked up a 2nd LM13700 as per so-called "SmallStone 13700" ( ) schemo (with 100n caps) after the "Sine-Sine_90" :


(click on pic for clip...)

shifting a ~10Hz sine back from 0° to ~ -355° and forth to 0° again with a single 100k pot...
channel1 is the fix 0° LFO-output, channel2 is the variable output from the 2nd stage of the 2nd LM13700,
into which the LFO was being fed...
(sorry for crappy clipquality coz of focus- and synchro-problems of the cam...)

The 2stage-shifter theory works perfect...

[R.G.]

The 2stage-shifter theory works perfect...

It absolutely does. The only thing wrong with that is that you must change the phase shift stage at the same time and by the same amount as you change frequency, or the phase shift of the two LFOs changes with settings of the frequency pot as well.

If Charlie's application is OK with adjusting the phase pot each time the frequency is changed, it is fine.

[puretube]

The 2stage-shifter theory works perfect...

It absolutely does. The only thing wrong with that is that you must change the phase shift stage at the same time and by the same amount as you change frequency, or the phase shift of the two LFOs changes with settings of the frequency pot as well.

If Charlie's application is OK with adjusting the phase pot each time the frequency is changed, it is fine.

I don`t think he wants to measure correlation, but rather wants to get some moving sounds 

[moosapotamus]

Damn! Need to get caught up on this discussion. Only skimmed it so far...

I have not had electricity in my home since this past Friday 12/12 ~1:30 AM, and can only get online a little bit during the day at work. Sub-freezing temperatures over the weekend with no heat left me homeless, sleeping with relatives. Now running a borrowed generator to power a few lights, TV and the pellet stove to keep warm. Had ~ 2" of snow this morning and expecting much more on Friday. No news on when power will be restored, hopefully by the weekend.

You guys are posting some verry cool stuff, tho. Please keep it coming. I'll get caught up when I can.

Thanks
~ Charlie

[R.G.]

I don`t think he wants to measure correlation, but rather wants to get some moving sounds 

In that case, we were done at reply #8.   

[Eb7+9]

The only thing wrong with that is that you must change the phase shift stage at the same time and by the same amount as you change frequency, or the phase shift of the two LFOs changes with settings of the frequency pot as well.

If Charlie's application is OK with adjusting the phase pot each time the frequency is changed, it is fine.

that's the whole point to using a PLL, the static phase offset doesn't need to be adjusted as LFO frequency is changed ... they're perfectly independent of one another ...

[R.G.]

that's the whole point to using a PLL, the static phase offset doesn't need to be adjusted as LFO frequency is changed ... they're perfectly independent of one another ...

Sigh.

I know that, JC. That's why I was haring off down PLL rabbit holes, verifying for myself that phase detectors work the way I think they do.

We have the following ways:
- microcontroller; does exactly what Charlie wanted, completely independent, etc., etc. and suffers only from its output being stepped digital by one of several methods and needing smoothing, and needing (simple) programming.
- various forms of digital synthesis in the form of counters; getting phase shifts set into the counters is hard, as it the interface from knobs.
- quadrature sine oscillators which are then mixed to a variable phase output using VCAs and trig identies.
- PLLs with offsets applied to their phase detectors; doesn't work because phase detectors (with the possible exception of that patented thingie) lock at fixed positions plus or minus an error term. The error term is small and deliberately so in all PLL work I can find, and driven that way by the feedback that makes a loop lock.
- sine oscillator followed by phase shift network to shift the result in an analog fashion; works fine, but phase shift and frequency are interrelated and it's a two-knob exercise to get a new setting.
- your magic solution which you won't reveal.

All of these have their issues, yes?

But I did come up with one that seems to work. I did come up with a workable solution that's phase sensitive, not frequency sensitive, with a PLL. It occurred to me that since PDs want to lock at a fixed place, let them. You're looking in the wrong place for introducing phase shift trying to inject it in the middle of the PD. Take the original sine wave, run it into a comparator against a variable reference voltage. Us the edge of the comparator output, which reliably is offset X degrees into the sine, as the reference signal to a PLL. Do it outside the loop.

Sine waves are deterministic. A given number of degrees will always result in the same voltage on a normalized sine wave. So as you vary the comparator reference, its output is a variable-duty cycle square wave depending on the reference voltage. The leading (or trailing!) edge is at a position in the reference sine wave's phase that is fixed by the relationship of the sine voltage to the reference. For the resulting offset sine, take the sine wave out of a waveform generator chip and run THAT into a comparator, too, or just use the square wave output from the chip if it's available at the same time.

Now you can whip in a PLL, use the PD to lock the leading edge of the square wave output of the waveform generator chip to the edge of the output of the reference comparator. If you've used something good - one of those Hogge or other edge detecting PDs works - your PLL will lock to the leading edge +/- jitter and loop error, which the world is busy trying to make small. And since that involves dragging along the sine wave from the waveform generator chip, you now have a single knob phase adjustment which tracks phase, and remains locked to the desired phase in the face of the frequency being moved around.

It even works in a simulator; even with an XOR PD if you use two monostables to force the duty cycles of the two square wave  signals to be the same (an XOR PD is duty cycle dependent).

So the net is - generate a reference signal from the reference sine wave which tracks at a phase offset, then lock to that. Worked first time.