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DIY Stompboxes => Building your own stompbox => Topic started by: Gus on July 12, 2013, 02:03:22 PM

Title: no trim 18VDC jfet circuit
Post by: Gus on July 12, 2013, 02:03:22 PM
(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=49398&g2_serialNumber=1)

Discuss
Title: Re: no trim 18VDC jfet circuit
Post by: SmoothAction on July 12, 2013, 02:07:59 PM
Thanks Gus! To the breadboard we go  :D
Title: Re: no trim 18VDC jfet circuit
Post by: WaveshapeIllusions on July 12, 2013, 02:41:09 PM
Interesting. So how would this do away with trimmers? I see that there is the use of voltage divider biasing, which I'm not certain does away with trimmers. I do see that the source load is higher than the drain load, that can make some differences. It definitely raises the voltage at the source.

Of course, what does it stabilize? Does it set it to a point in the transconductance curve? Does it set Idss to a consistent level? Does it set the drain voltage at the same point?

I don't want to come across as picking it apart though. It does go about things in a different manner. I'm juat not sure how.
Title: Re: no trim 18VDC jfet circuit
Post by: Bill Mountain on July 12, 2013, 04:23:07 PM
It's not the same as your design but my JFET "hack" is to use higher voltages so the tolerance is not as important.  My main concern is usually a boost without distortion.  Whether the drain is at 10, 15, or 20 volts makes not difference to me.  If I wanted distortion then that would be a different story.
Title: Re: no trim 18VDC jfet circuit
Post by: Bill Mountain on July 12, 2013, 04:24:32 PM
I guess to add to the discussion.  Is this design dependent on the type of JFET?  Does VGS make a big difference?
Title: Re: no trim 18VDC jfet circuit
Post by: midwayfair on July 12, 2013, 04:38:43 PM
<<<<<< Goes to back up any important recent posts before the forum crashes again.


:icon_mrgreen:

Does R4 really say ... 2000 MEG?  :icon_lol:  :icon_lol:
Title: Re: no trim 18VDC jfet circuit
Post by: CodeMonk on July 12, 2013, 04:45:22 PM
Quote from: midwayfair on July 12, 2013, 04:38:43 PM
<<<<<< Goes to back up any important recent posts before the forum crashes again.


:icon_mrgreen:

Does R4 really say ... 2000 MEG?  :icon_lol:  :icon_lol:

Thats the first thing I saw :)

Interesting circuit though.
Title: Re: no trim 18VDC jfet circuit
Post by: pinkjimiphoton on July 12, 2013, 05:08:21 PM
jeez, gus, 2gig resistors? do they even make 'em that high? holy shit!!  :icon_eek:

i finally got my printer loaded with ink, will start on the vero i worked up for your other design soon, Gus..

sorry to hijack the thread for a moment... this looks cool!
Title: Re: no trim 18VDC jfet circuit
Post by: armdnrdy on July 12, 2013, 05:14:19 PM
Quote from: pinkjimiphoton on July 12, 2013, 05:08:21 PM
jeez, gus, 2gig resistors? do they even make 'em that high? holy sh*t!!  :icon_eek:

Yes they do!

http://www.mouser.com/Passive-Components/Resistors/_/N-5g9n?P=1z0vkip

and they're very reasonably priced! $3.52 - $6.02!

about the same price as an enclosure!
Title: Re: no trim 18VDC jfet circuit
Post by: Gus on July 12, 2013, 05:29:48 PM
It is for a j201
http://www.fairchildsemi.com/ds/MM/MMBFJ201.pdf (http://www.fairchildsemi.com/ds/MM/MMBFJ201.pdf)
IDSS .2ma to 1ma
Vgsoff -.3VDC to -1.5Vdc

So Id is about 1/2 to 1/10 IDSS
The offset from the voltage divider can be .3VDC  to 1.5VDC higher at the source so the current in the 82K source resistor will not change all that much

8.5VDC/82k = .103ma
9.5VDC/82k = .115ma

Note the gain is set under 4

As the gain goes up you might want to adjust R2 and or R5 or R6

Yes 2000meg to show JFET can work with that gate resistor value.  Some jfet microphones have 1 to 2 gig resistors.  At that level you need to keep thing clean at the gate section of the circuit.   This is to just to show you don't need to limit yourself to 1meg.

With guitar effects you might want to try a 4.7meg gate resistor.

Other Jfets will need some different resistor values.
Title: Re: no trim 18VDC jfet circuit
Post by: pinkjimiphoton on July 12, 2013, 05:31:04 PM
dumb question, but why not just omit something that big? it's for all intents an open circuit at that high a resistance i'd think, i mean current leakage between nodes may be less than that on a pcb i'd think!!

that's HUGE! ;)

gus and i were chatting on the phone last week about these things and he said they could handle crazy high resistances.. i was thinking like 10 megs!! lol

Title: Re: no trim 18VDC jfet circuit
Post by: gritz on July 12, 2013, 06:47:34 PM
I fink the 2 giga-Ohms thing is a misprint. It's just tied to a faux ground at nearly V+/2, so it doesn't need to be particularly huge - the normal guitar / stompbox numbers should apply ok.

Unless the power supply is blameless the junction of R4 / R5 / R6 might like a capacitor to ground.
Title: Re: no trim 18VDC jfet circuit
Post by: Gus on July 12, 2013, 07:12:30 PM
It is not a misprint.  

I used a 2gig in the sim screenshot to show jfets can work with higher value resistors at the gate.  I am not suggesting to use a value like that in a guitar effect.

I did post to try a 4.7 meg

you can find 1 to 2 gig gate resistors in microphone circuits

I wanted to get a discussion going and it seems people have looked at and questioned the circuit fragment

You need the higher supply voltage to get R2 to act more like a constant current device

Yes a cap to ground at R4, 5 and 6 node would be a good thing to do.

It it good to read people questioning why or pointing out omitted things.
Title: Re: no trim 18VDC jfet circuit
Post by: toneman on July 12, 2013, 07:39:47 PM
So, gus,

with 18V, what is the maximum peak-2-peak before clipping?  (8Vpp?)

seems like one still has to tweek (trim) the voltage to find the spot on the load line to get the maximum signal swing.

you said your gain was "4", so 1Vpp in, is 4Vpp out....long way from clipping......

LOTS of headroom left!!

yeh,  2G resistors  :icon_eek:  :icon_eek:

yeh   EEK!

:icon_cool:
Title: Re: no trim 18VDC jfet circuit
Post by: gritz on July 12, 2013, 07:52:37 PM
Quote from: Gus on July 12, 2013, 07:12:30 PM
It is not a misprint.  

I used a 2gig in the sim screenshot to show jfets can work with higher value resistors at the gate.  I am not suggesting to use a value like that in a guitar effect.

I stand corrected Gus! But unless your source impedance is devilishly high (like a capacitor mic capsule) then it might be a bit excessive - and prone to thermal noise - a lot of of which won't get clamped by the source due to the small input cap, but will find it's way into the gate instead.

I guess it's ineveitable that geeks will end up micro - analysing the peripherals, rather than checking out the important stuff.

Interesting - I have  a +18V, -9V setup on my board right now with some J201 living in the +18V part. It didn't dawn on me to do a "long tail" or constant current thinger utilising the -9V rail to feed the fet sources. I have trimmers everywhere...

I think that coffee and tweaking is required here, so thanks. :)

Title: Re: no trim 18VDC jfet circuit
Post by: puretube on July 12, 2013, 08:08:12 PM
Sometimes the mentioning of "source" and of "source impedance"
in a FET-thread
kinda tries to confuse me...



Furthermore, sometimes threads about FETs make me wonder,
whether "Idss" and "Ids" is being regarded as expressing/depicting the same phenomenon?
Title: Re: no trim 18VDC jfet circuit
Post by: pinkjimiphoton on July 14, 2013, 08:10:12 PM
after the last build (gus's take on the ep style booster) i guess i gotta try this one, too.

gus makes some bloody amazing effects, for sure!

the OUSB is the sickest thing ever unleashed upon creation  :icon_mrgreen:
Title: Re: Re: no trim 18VDC jfet circuit
Post by: ch1naski on July 14, 2013, 09:14:57 PM
Ousb? Thread link? If pjp endorsed it like that, I gotta check it out;)
Title: Re: Re: no trim 18VDC jfet circuit
Post by: Lurco on July 15, 2013, 02:26:47 AM
Quote from: ch1naski on July 14, 2013, 09:14:57 PM
Ousb? Thread link? If pjp endorsed it like that, I gotta check it out;)
http://www.diystompboxes.com/smfforum/index.php?topic=27857.msg187779#msg187779
Title: Re: no trim 18VDC jfet circuit
Post by: WaveshapeIllusions on July 15, 2013, 03:35:19 AM
Oh....it just clicked for me. The source load is high enough that for the whole range of Vgs(off) it acts likes a constant current source. Genius.

So I'm guessing that we would want the lower resistor in that voltage divider to be the same value as the source resistor? Or wait... I'm trying to think of how to math this out. You figure out the source voltage, based on Vgs(off) ranges. Then you choose a resistance for the source load that makes that change minimal relative to Ids. Right?

Anyways, thanks for coming up with this Gus. :) Generally, the drain load is the larger of the two, so inverting it is very clever. Bypassing with a cap sets AC gain anyways, so it can be done without sacrificing gain. I wonder if we could combine it with that split source load biasing. I have much experimenting to do.
Title: Re: no trim 18VDC jfet circuit
Post by: tca on July 15, 2013, 05:33:19 AM
Glad you took a different, and better, path.

Cheers
Title: Re: no trim 18VDC jfet circuit
Post by: Gus on July 15, 2013, 06:29:29 AM
This circuit is not something I came up with.
You can find it in one of the Vishay jfet app notes. 
It is also in books
It is the same type circuit I posted in another thread that used  + and - supplies this one is for one supply voltage
It is also for the j201 because it seems to be popular at this forum
for a different jfet that has a different range of IDSS etc you will need to change the resistor values
For a jfet like a 2n3819 this type circuit might not work well because off the wide range of IDSS, Vgsoff etc.
The gain is set low to limit clipping
It should have a cap at the fixed bias voltage node as pointed out by gritz and a lower value gate to fixed bias node resistor 2.2meg to 4.7meg might be good to start with.

This circuit has limitations and I think jfets should be measured and selected for use in different parts of circuits.
Title: Re: Re: no trim 18VDC jfet circuit
Post by: pinkjimiphoton on July 15, 2013, 09:31:54 AM
Quote from: ch1naski on July 14, 2013, 09:14:57 PM
Ousb? Thread link? If pjp endorsed it like that, I gotta check it out;)


the best octave up...tracks the whole neck. almost unusable amounts of distortion.... crazy harmonics, sustain that jumps octaves as it blooms...

it's @#$%ing awersome. BUT... make sure you ground the cases of the pots together or it may oscillate!! a LOT of gain!!

if ya turn the gain control way down, you can get an almost "cleanish" octave up, too.

as with all of gus's circuits, major bang for the buck... low parts count, well and cleanly designed, and outstanding in use.

i mounted my sick box with a fuzzface in the same box. amazing combination of over the top.

sorry to hijack the thread again!!
Title: Re: no trim 18VDC jfet circuit
Post by: pinkjimiphoton on July 15, 2013, 09:34:59 AM
ousb demo

(https://www.youtube.com/watch?v=M5xy04XqJSA)
Title: Re: no trim 18VDC jfet circuit
Post by: PRR on July 15, 2013, 10:34:15 PM
> lower resistor in that voltage divider to be the same value as the source resistor?

No. Youse guys aren't looking or thinking. No wonder Gus gets so little response to his posts.

Let's simplify:

(http://i.imgur.com/Gp11l3n.gif)

Gus biased the JFET Gate to 8 Volts.

How he got there (82K, 2,000Meg) does NOT matter.

Why?

Because if we know the JFET Source voltage, and Source resistor, we know the JFET current.

But with a random-pick JFET, with Gate at zero Volts, the Source voltage can be zero Volts or 4 Volts.

But-But: with the Gate held up at +8V, we *know* the Source voltage will be 8 Volts to 12 Volts.

Which is not much of a variation.

The 8V pre-bias overwhelms the 4V uncertainty in Vgs.

Now with a 10K Source resistor, we *know* the current must be 0.8mA to 1.2mA. And for initial design, we can use "1mA" as a starting point.

We have stabilized the JFET current. We won't have a way-out result.

The 8V battery does not supply "any" current. And is awkward. It can be replaced with a Voltage Divider.

Going further:

We want a Drain resistor to take the output. The value has no (1%) effect on current, unless it is so large the Drain is pushed into the Source.

Source is at 8V to 12V. We should allow a couple Volts across the JFET. So the lowest Drain voltage should be 14V. Highest is 18V. Audio swings both ways. We want to split the difference. 16V. That's 2V down from 18V. We want a resistor that drops 2V at 1mA. 2K is our Drain resistor.

Just like that, we have a stable circuit. But is it an amplifier?? It has no current gain because we have a solid 8V battery tied to the Gate. But the Gate draws no current. It will bias the same if we stick a 100K, 1Meg, even 2000Meg resistor between the 8V and the Gate. Now we can put some signal into the Gate, and very-small current, while we have good current in the output. So good current gain. How about voltage gain? Just like this, the voltage gain is less than 2K/10K or 0.2, or a loss. However we can change the AC/audio voltage gain without upsetting the DC bias with a Source resistor bypass cap. Now the voltage gain depends on JFET Gm, so you need to interpret data, or just Try It.

The 2K output impedance is rather small, and gain improves with lower current (higher Drain resistor). Gus' choice of ~~40K will increase voltage gain significantly, while still giving a low-enough output impedance for general audio circuits.
Title: Re: no trim 18VDC jfet circuit
Post by: mistahead on July 15, 2013, 10:38:43 PM
That-thing-me-sideways...

I've been trying to understand these JFET tricks from Gus for a couple of weeks now and PRR - your rage offers clarity.

Props to both Gus and PRR - thanks!
Title: Re: no trim 18VDC jfet circuit
Post by: gritz on July 17, 2013, 03:14:58 PM
As I threatened earlier in the thread I headed of to the breadboard, where I had an overclocked ICL7660SCPA spitting out +18V and =9V which I figured would allow me to use (almost) the whole of the +18V for signal and not worry about creating faux grounds that might induce noise and increase component count.

So, the concept:

(http://i755.photobucket.com/albums/xx191/se7enpoint62/J201/201_concept_2_zps77b5129e.jpg)

Pretty simple really. We want the jfet drain to sit at V+/2, so Rdrain needs to drop 9V. As no current flows through the jfet gate in normal operation then we simply need to drop 9V across Rsource to achieve this - because an identical voltage will be dropped across Rdrain. Cbypass and Rgain are there to give us some AC gain and tonal shaping options. Within the bounds of the jfet's gm characteristic (and given a big enough Cbypass) the signal gain of the circuit will be Rdrain/Rgain. Very basically. As a ballpark, I've chained three fet stages and I'm using Cbypass of 470n  to rolloff bass and de-muddify and 470 ohm Rgain to flatten the passband, but more on this later...

However, two wrinkles conspire against us:

1) Due to normal fet operation the source will naturally sit slightly positive of 0V. This means that a bit more than 9V is dropped across Rsource and as an identical voltage is dropped across Rdrain our quiescent drain voltage will be a bit low. For our old favourite J201 fet it's not a lot, but it's there.

2) Our charge pump voltage doubler doesn't actually double the input voltage. The output voltage will actually be lower than Vin*2 to the tune of two diode drops. We can maximise efficiency by using Schottky diodes, but it will still be fractionally low.

Considering 1) and 2) above the obvious thing to do is to reduce our -9V a bit (technical term).

The hack:

(http://i755.photobucket.com/albums/xx191/se7enpoint62/J201/201_power_2_zps6dc10867.jpg)

This is the power supply I'm using. Schottky diodes D1 and D2 provide maximum positive oomph, while D3 and D4 reduce the negative rail voltage "a bit". D5 provides protection in the event that the load tries to pull the negative rail north of 0v.

The test circuit:

(http://i755.photobucket.com/albums/xx191/se7enpoint62/J201/201_test_2_zps9a23130b.jpg)

This shows teh numbers with some J201s that I have. Variations in the fets' VGS characteristic will be reflected by slight variations in the voltage in the source, but with the few that I had laying about the variation was a few tenths of a volt - not bad at all. Because of the high value of Rdrain the fet's drain can swing down to almost the same voltage as the source, so it's pretty close to the midpoint of the available voltage swing. If you're using fets with a higher VGS characteristic then you may need to reduce the negative rail voltage a bit further. However, with similar fets it's very repeatable and the 18V supply means that the odd volt here and there isn't a big deal at all.. If you want to set a different quiescent Vdrain (e.g. 2/3 Vsupply) then it's a simple matter of changing the source resistor to suit.

As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way. The noise performance is good and it's making musical noises, but as with any high gain circuit sensible power rail decoupling is necessary to prevent noise and instability (self oscillation). My current layout looks a bit like this:

(http://i755.photobucket.com/albums/xx191/se7enpoint62/J201/201_decouple_2_zps40ac8a1e.jpg)

Even with the very low value dropper resistors in the supply rails the noise performance and stability seem good so far - but it may require tweaking if it ever gets to the pcb stage. I also have some low value (470pf) caps between the fet drains and ground - because there's no point reproducing the stuff that you don't want.

And not a trimmer in sight.

Hats off to Gus for prompting this bit of research. :)
Title: Re: Re: no trim 18VDC jfet circuit
Post by: slacker on July 17, 2013, 03:41:14 PM
Nice work.
Title: Re: no trim 18VDC jfet circuit
Post by: tca on July 18, 2013, 01:15:14 PM
@gritz
> As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way.

How much distortion/OD can you get out of it? Any sound clips?

I've been playing also with gain stages but wit BJT's (3 stages also), I've found that a big cap 1000u in parallel with the power source is enough for killing any oscillations.

Cheers.
Title: Re: no trim 18VDC jfet circuit
Post by: gritz on July 18, 2013, 02:11:12 PM
Quote from: tca on July 18, 2013, 01:15:14 PM
@gritz
> As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way.

How much distortion/OD can you get out of it? Any sound clips?

I've been playing also with gain stages but wit BJT's (3 stages also), I've found that a big cap 1000u in parallel with the power source is enough for killing any oscillations.

Cheers.

Hi tca - sorry I haven't gotten back to you earlier, this is the first time I've checked this thread today.

There's a lot of gain available - more than overdrive, really. It's pretty metal when flat out. Give me a day and I'll post a (very work in progress) schematic and I guess I'll have to open another Soundcloud account for those experimental clips and whatnot.
Title: Re: no trim 18VDC jfet circuit
Post by: Gus on July 18, 2013, 07:19:43 PM
Looks good

I would have kept the more negative voltage and adjusted the Rsource resistor up a little in value.  The greater the voltage the more like a constant current device.
Title: Re: no trim 18VDC jfet circuit
Post by: gritz on July 18, 2013, 08:50:48 PM
Quote from: Gus on July 18, 2013, 07:19:43 PM
Looks good

I would have kept the more negative voltage and adjusted the Rsource resistor up a little in value.  The greater the voltage the more like a constant current device.

Yeah, that would work too - I was just keeping the resistor inventory down and reducing the need for actual maths!  :icon_lol:

Substituting different J201s shows that it's pretty robust in it's handling of varying Vgs. My biggest initial worry was noise, but it's proved to be sweet - despite the fact that it's a total rat's nest on my breadboard.
Title: Re: no trim 18VDC jfet circuit
Post by: Gus on July 20, 2013, 09:58:33 AM
gritz

I put your circuit into Lt spice to check the sim voltages against a real build I used +18VDC and -9VDC
(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=49458&g2_serialNumber=1)