I'm continuing to learn about all this stuff as I'm working on building a clean boost for my bass. I had it working very nicely when I had passive pickups in the bass, but then put in active pickups and the signal is clipping. It actually produces a pretty decent overdrive tone, but it's not what I'm going for. I tried various resistor values, but that didn't help.
Here's the circuit I built from Tonefiend http://www.tonefiend.com//wp-content/uploads/DIY%20Club%20Project%203%20v02.pdf
In place of the potentiometer, I have a 470 Ohm resistor. I'm using a different JFET, don't remember which one off the top of my head, but it's rated at 6V.
(https://s9.postimg.org/fqi11z0qj/Screen_Shot_2018-03-11_at_9.26.52_AM.png) (https://postimg.org/image/fqi11z0qj/)
My question is, would a JFET with a higher voltage rating solve the problem?
While your waiting on a more complete answer it may be worth trying a 100k pot or resistor on the signal input path, as seen on the Zvex Mastotron).
I'm no authority on the subject but I understand believe this feature (at least on the mastotron) was to make the pedal play better on Active pickups. Possibly.
If I had my choice, I'd add a source resistor and run this on 12V or 18V for max clean headroom.
Designed like this: http://www.runoffgroove.com/oldfetzer.html (http://www.runoffgroove.com/oldfetzer.html)
Thanks y'all! I'll try these out. The Old Fetzer looks nice and simple, and I think I have all the parts laying around. I'll look into the Mastotron too.
> In place of the potentiometer, I have a 470 Ohm resistor
Why? ? ?
Why not try it as-published, instead of random values?
470r is awful low for most JFETs. It also is a HEAVY drain on a battery. There is a reason the designer drew a pot there. Try it.
In general though, that isn't an all-purpose bass/guitar preamp. The JFET is zero-biased, nearly hard-on. You can get a little more current by forcing the Gate positive, but in most instrument situations that lust leads to clipping. Agree with the other guy: there is usually a Source resistor, and such plans are easy to find.
Quote from: PRR on March 12, 2018, 12:56:54 AM
> In place of the potentiometer, I have a 470 Ohm resistor
Why? ? ?
Why not try it as-published, instead of random values?
470r is awful low for most JFETs. It also is a HEAVY drain on a battery. There is a reason the designer drew a pot there. Try it.
In general though, that isn't an all-purpose bass/guitar preamp. The JFET is zero-biased, nearly hard-on. You can get a little more current by forcing the Gate positive, but in most instrument situations that lust leads to clipping. Agree with the other guy: there is usually a Source resistor, and such plans are easy to find.
Thanks for the tips. As a relative newbie I appreciate them...
The guy who published it has the pot in there to help identify the appropriate resistance to get the most boost out of the JFET. It's not meant to remain in the circuit. After having the circuit work well with my passive pickups and in an attempt to learn more about how all these things work, I tried a bunch of different resistor values to see what effect they had on the gain to see if I could get a boosted clean signal that I liked. I couldn't...so here I am... :-)
Seems like there are definitely better circuits out there. This was a good entry to begin understanding how all these components work together. I look forward to building the Old Fetzer and hopefully gain even more understanding.
QuoteIf I had my choice, I'd add a source resistor and run this on 12V or 18V for max clean headroom.
Designed like this: http://www.runoffgroove.com/oldfetzer.html
I third adding the source resistor.
Shouldn't be a Gate bias resistor somewhere there..??
Quote from: antonis on March 12, 2018, 05:39:28 AM
Shouldn't be a Gate bias resistor somewhere there..??
Pulldown?
Quote from: GibsonGM on March 12, 2018, 07:57:23 AM
Pulldown?
You may call it as you like, Sir... :icon_redface:
I can't see in OP schematic neither IN coupling capacitor nor Gate bias item so I've to suppose a direct DC coupled zero Volts booster..
Quote from: antonis on March 12, 2018, 09:16:38 AM
Quote from: GibsonGM on March 12, 2018, 07:57:23 AM
Pulldown?
You may call it as you like, Sir... :icon_redface:
I can't see in OP schematic neither IN coupling capacitor nor Gate bias item so I've to suppose a direct DC coupled zero Volts booster..
Yes, the schematic the OP posted seems to be missing some things! It will only amplify positive parts of the signal, because it is not 'elevated'.
I meant this one: http://www.runoffgroove.com/oldfetzer.html (http://www.runoffgroove.com/oldfetzer.html) which has the 'missing parts'
The OP schematic does not seem like it would give a very 'clean' boost! :)
IMHO, the 68k resistor on Fetzer Valve is some kind of "residual" from original Fender tube input stage..
(grid stoppers were used mainly to prevent blocking distortion when input tube grid voltage becomes more positive than the cathode voltage - and also prevent very high freq oscillation by forming a low-pass filter together with Grid-Cathode interelectrode capacitance..)
Some FETs work well with such a series resistor (of much lower value, e.g. 1k) but it shouldn't happen anything if you omit it..
P.S.
Why you tease me to write things you already know, Sir..?? :icon_mrgreen:
No teasing, Antonis! My hope is to move Buddy over to the Fetzer, so he can see how it "should" be designed. Not to say the original circuit is "bad", but it seems to be kind of "off", doesn't it? You noticed that it has no bias...Runoffgroove has provided us with a very easy way to fix all of this!
I have to agree, the 68k is very familiar to Fender people :) Maybe it is there to build the Fender spirit into the FET? Ha ha.
Quote from: GibsonGM on March 12, 2018, 12:11:36 PM
Maybe it is there to build the Fender spirit into the FET?
:icon_biggrin: :icon_lol: :icon_biggrin:
Maybe yes..
If "spirit" could only depend on transconductance.. :icon_wink:
A few questions...
1. Gate bias resistor...help me understand...this is a resistor before the gate (base) that, along with other resistors biases the voltage of the transistor. i.e. They set the operating voltage/current of the transistor? Am I understanding correctly?
2. In the Old Fetzer schematic, is the 1M pull down resistor acting also as a biasing resistor?
3. How does one go about determining/calculating the values of resistors used to bias a circuit like the Old Fetzer?
Actually, the original circuit I posted was a great very clean boost, with way more boost than I needed. It worked great with my lower output passive pickups. Not clean with my high output EMGs...
I gotta pick up new soldering iron tips, hopefully I'll get the Fezter built and working in the next day or two.
1. Yeapp.. :icon_wink:
2. Yeapp.. :icon_wink:
(without "also"..)
3. Only from desirable Input impedance.. :icon_wink:
(also restricted by leakage Gate current to not be significally off-set..)
If there is Source resistor, like in Fetzer Valve, Gate is set to GND via 1M resistor and Source is set a couple of Volts more positive than Gate via Source resistor voltage drop due to Drain-Source current..
(FETs should work almost predictably in such a way - but there often are surprises..) :icon_wink:
The source resistor you see on the Fetzer is actually there to 'elevate' the gate by a few volts...this sets the gate to be in the "middle" of the supply voltage (sort of). This is the FET equivalent of the cathode resistor in tubes. Here is where it gets dodgy!
Read (I should have posted this link instead of the 1st one!) http://www.runoffgroove.com/fetzervalve.html (http://www.runoffgroove.com/fetzervalve.html)
There is also this, very informative: http://diy.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm (http://diy.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm)
The above 2 pages have solved the bias problem, and my talking much about it will only serve to confuse you :)
In a triode gain stage, like a REAL Fender amp, you use the tube curves from the data sheet to find an 'optimum' (for you) bias point. This is set such that the input signal can rise above AND below this point, so the negative swing of your signal can also be amplified. They do it a little differently with FETs, but it is very similar, too, and as Antonis noted - the Drain > Source current is what makes this happen. The 1M pulldown is really so the gate can confidently know that THIS POINT is ZERO VOLTS (ground). The FET does the rest...the tutorials explain how.
I really have no inkling how your original circuit sounds clean, but if you say so, I will believe you. It can't amplify the negative excursions of an input signal...it's clipping them. Probably sounds good, LOL...since the source is referenced to gnd. Maybe the gate floating like that has some effect, I dunno. Anyway, if you liked it, you'll probably LOVE what ROG and Smallbear have to offer! Especially if you tried TWO stages, in cascade, with a 'gain pot' in between, with a bypass cap only on the 2nd stage (or not at all)....if you don't want nasty clipping, having a small gain for each stage and the ability to control the 2nd stage will make a big difference, IMHO. Smallbear is showing something a bit like this low on the page, more for adding a tone control, which you could simply omit and use a pot in there.
> It will only amplify positive parts of the signal,
No, with a full study, it turns out to be a fine small "clean" amp. The Gate _can_ go positive, but at +0.6V it sucks huge current, and 0.4V-0.5V may be real heavy load in a guitar chain. It also goes negative just fine. The result seems to be that a 1+V peak-peak input makes a 2.5V p-p output, of such limited swing (around the very high 5mA biaspoint) that THD may be just a few %. So a mild boost.
(https://s18.postimg.org/9z0cidk1x/2_N5457-470r.gif) (https://postimg.org/image/9z0cidk1x/)
IMHO, 470R load line slope should be wider (upper part closer to Id axis) leading in FET working into "linear" region (variable channel resistance) for VGS slightly above -500mV, say..
(just a guess/feeling of course - influenced perhaps by parameters wide spread.. )
Really, Paul? I threw it in LT Spice. As I increased Rd (I first began with a higher Rd, hence my clipping negatives statement), I got positive spikes (well amplified) and clipping the negatives at around .6v or so. Dropping Rd to 1k or so did result in a well-shaped wave, lower values good shape but still offset....still nothing crossing below zero for the obvious reasons...kind of thinking, how does the next device (or amp) deal with this? Something I've never looked at. But I do see that low Rd will get you a good wave form.
If you forward bias the gate if a JFET, you will start pushing current through the junction as if it were a forward-biased diode, assuming it doesn't simply burn up. So, yes, clipping* will occur due to this diode effect. Still, not a great idea to do this because JFETs don't fail in visually stunning ways like electrolytic caps do, making it a rather dull experiment. :icon_wink:
*Edit: I realized I didn't paint the complete picture here. When you forward bias the gate, you are also injecting current into the channel, further increasing the drain current almost as if the channel were more open (just an illusion), but this gate current isn't modulating the drain current like in a well-behaving amplifier, but rather adding to it. Also, input impedance drops dramatically.
Edit 2: I was quite wrong in my analysis. :icon_redface:
See below. :icon_biggrin:
What I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset. Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device? Honest question, it's not something I've dealt with.
Now you confused me, Mike.. :icon_cool:
An AC signal riding on a DC offset is exactly what we intend to do..
(DC bias Base/Gate/OP-Amp input ridden by AC signal.. - superposition..)
Direct signal coupling (no DC offset/elevated signal voltage) is mostly used on symmetrical bi-polar supplies, where signal swings almost equally above and below zero volts..
(you may call it "floating" due to no real grounding..)
Perhaps, I didn't get what you really wonder about.. :icon_redface:
Quote from: GibsonGM on March 13, 2018, 08:36:34 AM
What I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset. Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device? Honest question, it's not something I've dealt with.
I'm not sure I completely follow your question. I assumed that the input was at 0VDC and therefore does cross zero.
In addition to self-biasing, like you describe, you can bias a JFET without a source resistor by applying a negative DC offset to the gate, e.g., instead of a gate resistor to ground, you could have a gate resistor to some negative DC source.
I believe that Mike managed to confused us both, Eric, and happy ever after gone for his beer... :icon_lol:
Quote from: antonis on March 13, 2018, 08:57:03 AM
I believe that Mike managed to confused us both, Eric, and happy ever after gone for his beer... :icon_lol:
It is day time here, Antonis, 1:30PM...I do not drink beer before 5 PM :) Perhaps I NEED to drink a beer!
I took another look (simulation). I didn't add a load resistor after the output cap :P So that left my output floating. So the final output was showing as a sine wave from .5V to 3V or something like that...offset.
Adding a 50k after it made the circuit behave normally. :icon_redface:
Be fair to me - no load is given on the original schematic! :icon_mrgreen: But I should have known better. The load would be the amp or the next pedal. So yes, the circuit is a nice clean boost. I will be quiet now.
Did you add any source impedance for the sine wave input in your simulation?
Thanks Fellas!
I leave the theoretical debate to you guys, that's way above my pay grade at this point... :-)
I built the Fetzer boost on a vero board and it's working quite well! If the volume on my bass is up too high, I still get a little clipping. I'm realizing just how hot the output is from these active EMG pickups. They're way hotter than my other active basses, so as long as I run at 50-75% volume on my bass, I'm good.
I couldn't have done it without y'all and I appreciate the links! I'll spend some time reading those pages and trying to digest it all.
Cheers!
Quote from: EBK on March 13, 2018, 02:55:22 PM
Did you add any source impedance for the sine wave input in your simulation?
In series, or shunt? I'm assuming maybe 100R in series, to mimic the output Z of the guitar or other source? I built the circuit as shown. I left the output floating - my bad!
Glad it's working out, Buddy! There are tricks to attenuate at the input and allow you to have your volume on 10...such as a voltage divider (noisier) or using a FET with a higher Vp (pinch-off voltage), or pop in a different 2N5457 if you have one, see if there's a difference.
With the Fetzer, you can increase the source resistor to lower the gain...it affects the bias in some ways too, tho, so it would be a "by ear" thing.
QuoteWhat I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset. Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device? Honest question, it's not something I've dealt with.
It's actually a valid thing to ponder.
I remember this coming up about 18 years ago on the sci.electronics.design news group. It didn't get answered. Trusting spice for answers might be wrong because the model needs a 2D distributed model of the gate diode **.
- If you have Vds at the drain and Vs=0 then there is a gradual drop of voltage down the channel.
- The gate looks like a distributed stack parallel reverse diodes from drain to source.
- The "diode" nearer to the source has the least potential across it.
We speculate that this diode has a low reverse bias, passes the most current and hence
probably ties to the gate to the source more than anything. So that means something
more like Vgs = 0.
Another thing to ponder is if you have just the channel it looks like a block of silicon and acts like a resistor. Does placing the gate there affect things? When we add the gate it has p-material which sucks out a small region along the gate/n-channel interface. So that would make the resistance a little less than the raw silicon block. As the gate becomes positive, due to an AC voltage modulate the gate, it would reduce that suck-out region and decrease the resistance.
It's not a simple situation.
[Edit: ** On the other hand it's like this for the normal JFET case where the spice equations work.]
Quote from: Rob Strand on March 13, 2018, 07:15:06 PM
As the gate becomes positive, due to an AC voltage modulate the gate, it would reduce that suck-out region and decrease the resistance.
Can we just stick with n-channel depletion-mode JFETs for now? hmm....
Awesome Rob, LOL!
To cut it right to non-theoretical...WHY NO SOURCE RESISTOR IN THE ORIGINAL? Doesn't the Rs give the thing more functionality, gives the designer more control?
My Apologies for a stupid post.
I'm having a sleep deficit day.
I've misread source resistor for gate resistor.
Post fixed.
QuoteTo cut it right to non-theoretical...WHY NO SOURCE RESISTOR IN THE ORIGINAL? Doesn't the Rs give the thing more functionality, gives the designer more control?
Gate resistor: When I see that type of thing I always assumed the source, being a guitar or other, has a DC path to ground and provides a DC path for the gate, like the gate resistor. By not adding a gate-source resistor you aren't loading the source. Obviously won't work with a Piezo source which is capacitive.
Source resistor: Not sure
- Naive design
- Delibrate. Using high current for low noise. Also Vgs=0 allowed since assuming very small input signals.
QuoteDoesn't the Rs give the thing more functionality, gives the designer more control?
It lets you get more input signal swing before the gate-source diode become forward biased.
Beyond that you can control the gain (both for bypassed and unbypassed cases). You can see some of the advantages of adding a source resistors in the Biasing J201 thread I posted a few weeks back.
[Edit: Not to mentioned reducing the operating current.]
For spice, maybe connecting 10 JFETs (with 1/10th Rds) in series with the gates tied together will give some confidence to the results.
Maybe not that simple. That's only going to re-inforce the theory. We need to choose a correct VP that reflects physics, not thoughts!
I finally understand (mostly) that booster circuit, thanks to a one-page IEEE paper from 1964. A low-res version is available at this link: http://ieeexplore.ieee.org/document/1445202/
The important bit is:
QuoteAs the gate-to-source voltage is increased a number of effects will occur. When the gate voltage becomes sufficiently positive appreciable current will start to flow in the gate-to-source circuit, and, if the p gate is relatively highly doped compared with the channel, holes will be injected into the channel, causing, through conductivity modulation, an increase in the conductivity of the region represented by R1. .... The diode-resistance network then assures that as the gate voltage is increased the resulting gate current will be distributed among the diodes.
The "
R1" and "diode-resistance network" are in reference to a DC equivalent circuit model illustrated in the linked paper that is pretty close to the diode model Rob described.
So, I now also understand what Rob already correctly described above! :icon_cool: :icon_lol:
Now, please excuse me while I place strikethroughs in the incorrect stuff I previously posted. :icon_rolleyes:
Hey, glad I'm not alone in looking at this and going "WTH??", he he. We're having a big snowstorm here in the arctic, and I haven't slept much for 2 days (good excuse). There are no stupid posts, we just have moments of conflict - what we know vs. what we think we know, assumptions, etc. To me, that original thing looked almost DC coupled, simply because of the 'missing' Rs. JFETs are different!
Quote from: GibsonGM on March 13, 2018, 05:34:45 PM
Quote from: EBK on March 13, 2018, 02:55:22 PM
Did you add any source impedance for the sine wave input in your simulation?
In series, or shunt? I'm assuming maybe 100R in series, to mimic the output Z of the guitar or other source? I built the circuit as shown. I left the output floating - my bad!
Series, yes. As the gate voltage increases in that positive input region, the input impedance of that circuit drops exponentially. I would expect input source impedance to become quite significant
and result in squashing the negative half of the booster's output (a bit like asymmetric compression, which could be quite interesting), unless that is somehow balanced out by that conductivity modulation phenomenon.Nevermind. I believe I am wrong again because I was still thinking of a normal JFET....
(without interpreting semiconductor physics..)
With VGS slightly positive, we get maximun Drain current, depended only on channel resistance and VDD (assuming grounded Source..).
Channel resistance should be considered constant from now on.. (due to the limit minimizing of depletion area)
Any further Gate-Source positive voltage raise should result in no further current raise..(gm is practically vanished..)
(at least, not proportional to VGS anymore - Gate to Source forward biased junction current simply adds to Drain current and not amplified in any manner and should be restricted someway, e.g. with a series resistor..)
When VGS starts to be negative, Drain current "follows" it in a proportional manner (gm starts to "exist"..)
If so, we might have amplification on both positive & negative waveforms but, for sure, not undistorted..!!
Or do I suffer from another brainstorm..?? :icon_redface:
The problem is that the jfet stops acting like a jfet, mathematically speaking, once forward biased. In other words, you need a new model and formula (with a gate current term) to explain why the channel conductivity continues to increase. If I understand things correctly, you essentially get a small window of psuedo-BJT (I don't know what to call it) operation, limited by how much power your jfet can dissipate before it fails.
QuoteI finally understand (mostly) that booster circuit, thanks to a one-page IEEE paper from 1964. A low-res version is available at this link: http://ieeexplore.ieee.org/document/1445202/
Thanks, *extremely* cool find.
There's got to be a region where the Vds drop leaves some of the top diodes reversed bias and the bottom diodes forward bias. The top would act like a JFET and the bottom maybe like the transistor Cobbold speaks of. So maybe a cascode model will work. In an amp ckt I suspect you can only get in this region with low drain resistance values.
The author Cobbold is a famous dude. He wrote one of the JFET "bibles".
Some day I hope to understand what you all are talking about. :-)
You know what, the more I think about the transistor action the less I believe it. I believe the macro effect but not the mechanism. Fig 2 in the paper shows the gate current increasing but the gain is *dropping* almost in proportion. It's like there is a weak mechanism increasing the drain current by only a small amount despite the large increase in the gate current.
What I suspect really going on is when the gate forward biases it removes the lower part of the channel. Imagine a line across the channel where that part of the diode, and diodes below it, are conducting. The potential at that point becomes positive. That makes the JFET look shorter. With VDS present, normally the top part of the JFET channel is partially closed off. When forward gate biasing occurs VDS is applied over a shorted region of the channel and this moves the partially closed part of the channel up towards the drain, chopping of less of the channel and allowing more drain current to flow. Also, the effective VDS is reduced, as the JFET sees the VDS' where is the internal source point but S is the external source terminal.. Because of the forward bias S' is at a higher voltage to S.
Quote from: BuddyPrince on March 14, 2018, 07:18:39 PM
Some day I hope to understand what you all are talking about. :-)
Since
we haven't even fully figured out what we are talking about yet, I'd say you are pretty well caught up. :icon_lol:
OK I did a quick test in spice.
* Two JFET cases *
1) Nothing special. single JFET, params tweaked to give roughly same curves as Cobbold for normal case.
2) Split JFET into three series JFETs (top/middle/bottom). VP the same in each case as a first order approximation (VP depends on channel width).
* Results *
I(R1) is Id for Case 1 - Red
I(R2) is Id for Case 2 - Green
x-axis is VDS
The currents and voltages are as per the Cobbold paper.
The only difference is the normal case has a Vgs=0 and the forward case has an Ig=0.
Normal Case (gate reversed biased)
(https://s14.postimg.org/eflms906l/jfet_2n2498_gate_normal.png) (https://postimg.org/image/eflms906l/)
Forward Gate Case
(https://s14.postimg.org/45j7t1cvx/jfet_2n2498_gate_forward.png) (https://postimg.org/image/45j7t1cvx/)
* Models Used *
Single JFET
*2N2498 - Hacked to match Cobbold paper for normal case
* Idss = 2.5mA, Vp=2.7; beta = Idss/Vp^2
.MODEL JP2N2498RX1 PJF(VTO=-2.0 BETA=601u LAMBDA=0.013 RD=1m RS=1
*+ CGS=10p CGD=10p IS=9.48E-15 )
* ** RJS 15/3/2018
Three JFETs connected in series, with gates tied together (top/middle/bottom).
Bottom JFET has RS=1 like single (remnants of playing around with RS)
Use the following three "hacked" models
.MODEL JP2N2498RX1_3A PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=0.1m RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )
.MODEL JP2N2498RX1_3B PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=0.1m RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )
.MODEL JP2N2498RX1_3C PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=1 RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )
* Comments *
- Not a lot of difference achieved by splitting the JFETS (I did try 10JFETs).
- The sloped parts at higher VDS are slightly different. This behaviour is set by Lambda.
I can play with Lambda but the key point is the shape of the curve is different.
- The forward case behaves slightly differently. Id is a few percent higher for the split JFETs
- The currents in the forward case are smaller than the Cobbold paper and we do not see the big
Id step for Ig=10mA. The currents are however in the ball-park.
I suspect the JFET diode model, which determines Vgs, has something to do with it.
The real junction might have a softer characteristic and the ohmic series resistances will
probably have a much more complex behaviour (such as spreading).
Also we cannot change the softness of the diode knee in spice
Changing the diode model can move the drain current up and down but it cannot stretch the 10mA case.
All this is doing is changing Vgs set by the diode drop at a given diode current Ig.
- The case were Ig=0 produces a slightly higher current than the Vgs=0 case. In effect Vgs is slightly
positive when the gate is left disconnected (maybe Vgs = 200mV into forward bias).
Other than the split model, this doesn't add much to the physical understanding. It does highlight
issue modelling the Vgs diode under forward bias.
[Edit: The differences are due to splitting the diodes and lambda.]
I bent my snow-blower, but it still doesn't go off-track as far as you guys did.
The "limit" on JFET gate voltage is not zero but forward-diode, >0.5V. Nothing happens "at zero". The channel current continues to increase along the same curve as negative voltages.
If Vto is like 3V, another half-Volt is not a big deal, so this area is not usually used.
If you do use it, you must look at how positive you want to swing and how strong the signal source is.
_NO_ real signal is Infinitely Strong like a SPICE voltage source.
A guitar is at least 5K in bass and higher in treble. With pots and all, 50K may be a good approximation. Not of the actual with-guitar effect, but to show if your SPICE sim is totally lying to you (giving a right answer to your wrong question).
Take 50K and assume 1V peak guitar signal. That's less than 0.020mA.
The problem of course is that the forward diode will load-down the guitar on positive peaks. But up to 0.5V peak, not very much. However after experimenting with several JFET models I am unsure what the true gate current is. Adding a dumb old 1N914 diode G-S gives 11uA current at 0.5V peak, giving slight reduction which may be inoffensive on guitar.
The negative swing is the generally-understood quad of the JFET and will work fine.
So *for 0.5V signals* the zero-bias mode works "OK". We do not need to resort to old parchments speculating on more extreme gate abuse. 0.011mA gate current into channel working at 1mA-10mA, the gate injection is quite negligible.
The "problem" is that Idss of a same-number JFET will vary 3:1, the drain voltage is very uncertain. Some parts will bottom, others will top-out. Every one will clip different. Adding a source resistor allows this variation to be greatly reduced.
Anyhow... Here's the dubious SPICE plot of a JFET in the positive gate region. "Nothing happens" at Zero Vgs. Things keep climbing to 0.6V. Plotted at this scale, there's no real deviation to 0.8V (which may be a mis-model). Over 0.9V the gate current soars, all that flows to Source, and Drain current falls-flat.
(https://s18.postimg.org/dtexiyebp/JFET-zero-plot.gif) (https://postimg.org/image/dtexiyebp/)
So for "small" signals, zero-bias is not a sin.
For the "amplifier": I got quite a few different results with different SPICE models. All seemed dubious for Gate current so I stuck the diode on. The input distortion for 10K and 0.5V peak is visible but mild. The gate current is plotted *1Meg otherwise it would not show. The Drain voltage is not "centered" but this will vary about directly with Idss, and with Rd. The gain for these conditions is quite low. Actually <1 for this model, ~1.5 for another. The DC-blocked output of course follows the Drain voltage without the DC content.
(https://s18.postimg.org/ifb1rbfad/JFET-zero-amp.gif) (https://postimg.org/image/ifb1rbfad/)
KA7OEI's tests on a real JFET (http://ka7oei.blogspot.com/2015/09/):
(https://2.bp.blogspot.com/-mo6UIvXYEfw/VgmsKeWx3CI/AAAAAAAABP8/OisodQmWy1Q/s640/fet_gate_current_1b.jpg)
"As can be seen, as the gate-source voltage increases, the drain increases linearly - even after the gate-source diode junction starts to conduct: In fact, there does not appear to be inflection of the drain current curve when this happens!"
Quote from: BuddyPrince on March 14, 2018, 07:18:39 PM
Some day I hope to understand what you all are talking about. :-)
So do some more advanced DIYer's than you or I, Buddy! :) Lucky for us, most of the VERY in depth stuff going on here isn't required to design and build really nice stuff. Truthfully, we can do pretty well working with designs that have already been done for us.
Paul, posting above, has often talked about the VERY convenient fact that most all of what we're working with has been exhaustively put together, improved upon, and is all right there for us to.....umm, borrow, ha ha. Why would we re-invent something that was made 40 years ago, and works great?? We can tweak it, and make it sound how WE want it to, but the guts are already all set.
For good or bad, most of what myself and many others have done is learn the BASIC setups for each class of active device (mostly)...BJTs, opamps, jfets/mostfets, and tubes (triodes mainly). Just take an easy circuit, like an LPB-1, and learn how that works, and what happens when you alter some of the components that affect bias, and so on. Then find out how an opamp amplifies, how it is biased, how it is used as a buffer...same for mosfets, jfets. Yes, you'll make mistakes, or get into conversations where you look at little....foolish, over something you might have missed, but nobody here will give you (too much) hell over it.
You don't have to be Einstein to be able to WORK with these things, and you don't need to understand them at an atomic level, LOL! It's daunting at first, but after a little while you will see how things repeat, how parts of circuits can be blocked out as something you can understand, and in little time it stops being a collection of "WHAT IS THAT?" and becomes "OK, they put a tone stack in there, followed by a gain stage". Keep asking and learning, and shortly you'll be whipping up your own stuff, I guarantee it. Maybe later you'll want to explore the intricate characteristics of these devices, which can be fun once you are very far inside.
QuoteThe "limit" on JFET gate voltage is not zero but forward-diode, >0.5V. Nothing happens "at zero". The channel current continues to increase along the same curve as negative voltages.
The bottom line is as Vgs becomes positive Id continues to increase past IDSS, yet still closely following the usual square law. There's no kink from the perspective of Vgs vs Id. If however if there is a finite source impedance the gate-junction with limit Vgs and that limits Id. The open gate case is close to but not exactly the same as Vgs=0.
Interestingly Triodes behave quite similar to JFETs. The triode grid diodes are a lot softer than the JFET diodes.
That affects how the diode interacts with the source impedance.
IIRC, the Peavey transtube ckts use transistors and diodes.
For MOSFETs, Id keeps increasing as there's no diode.
Quote from: PRR on March 16, 2018, 09:12:10 PM
I bent my snow-blower, but it still doesn't go off-track as far as you guys did.
There's an important difference: If you push a JFET backwards, you just risk losing a JFET, but if you push a bent snowblower backwards, you risk losing a hand. :icon_razz:
In JFETs: If Oxner didn't teach it, it isn't worth knowing.
Oxner knew his salary depended on Siliconix selling a lot of JFETs, so he told every useful thing. (Evans was his boss.) Siliconix did eventually fail, but not for lack of trying.
Oxner does mention why forward Ig curves are rarely given. I suspect they only had a uni-polar supply handy, and taking forward curves would require wire-switching, and why bother? The reverse-bias Ig numbers are SO much prettier (albeit along the same line). They set the JFET apart from the sucky BJT.
(https://s18.postimg.org/5sa1a44jp/JFET-forward-gate.gif) (https://postimg.org/image/5sa1a44jp/)
Oxner gives "typical" Ig curve to 0.360Vgs. Extrapolating we get 1uA at 0.6V. So JFET gate diodes are about 1000X less conducty than BJT diodes. At 1uA, Shockley teaches 26,000 Ohms diode impedance. Low for geetar, but 0.1uA gives 260K, and that would be 0.54Vgs. 0.50V would be near 0.025uA and 1Meg. So a +0.5V forward bias is still High-impedance by guitar standards. Especially since it is higher yet at 0.45V and dynamic music will be lower most of the time.
QuoteOxner gives "typical" Ig curve to 0.360Vgs. Extrapolating we get 1uA at 0.6V. So JFET gate diodes are about 1000X less conducty than BJT diodes. At 1uA, Shockley teaches 26,000 Ohms diode impedance. Low for geetar, but 0.1uA gives 260K, and that would be 0.54Vgs. 0.50V would be near 0.025uA and 1Meg. So a +0.5V forward bias is still High-impedance by guitar standards. Especially since it is higher yet at 0.45V and dynamic music will be lower most of the time.
That's a good point. JFET are often used as low-leakage diodes. It follows that for a given voltage the diode current is lower. I extrapolated the graph the other way and hit about 1x10^-14 A which is quite typical for a JFET diode.
The slope of the graph gives the hardness of the diode knee, which is a little softer than a BJT. (At higher currents the ohmic effects come into play. Which is probably part of what we see in Cobbold's 10mA case.)
Quote
I suspect they only had a uni-polar supply handy, and taking forward curves would require wire-switching, and why bother?
It's easier/more accurate to feed in current and measure voltage.