Hello!
I've done some posts already regarding the construction of a phaser, for my college, based on the phase 90 by MXR. I've already studied everything and understood as much as I could.
As I am doing simulation of the circuit of the phase 90 on LTSpice, just to experiment with what I'd like to change, (circuit is shown on the figure below)
(https://i.postimg.cc/pmkPnQxx/testephaser3.png) (https://postimg.cc/pmkPnQxx)
I noticed that when I'm using the 2N5486 JFET's (because Spice doesn't have 2n5952 or 2n5457), I only have room for 0.3 Volts of sweep.
What I mean by that is that, with the bias voltage at 1.1 (given that the 2N5486 is written to have -4 VGScutoff, then 1.1 minus 5.1, which is the reference voltage, equal -4 VGScutoff), I have the results shown correctly with the calculations I made (with the parallel of the resistance of the filter being 24k ohm).
Now when I change the bias voltage to 1.4 Volts, the results show this:
(https://i.postimg.cc/vcNz8kxd/testephaser.png) (https://postimg.cc/vcNz8kxd)
And when I change the bias voltage to 1.5 Volts, the results show the following:
(https://i.postimg.cc/ZB4PDh26/testephaser2.png) (https://postimg.cc/ZB4PDh26)
Which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.
This makes absolutely no sense. Could it be that these JFET's don't work for this matter? Or am I doing something wrong? would highly appreciate any help regarding this matter.
Greetings,
Frederico Vilar
If you doubt the JFET is working you need to verify the JFET model.
Set-up an AC input voltage of 1V driving a voltage divider with a single resistor, JFET from divider output to ground, and set the gate voltage to a known value.
Roughy,
- R1 = 200 ohm, Vgs = 0V
- R1 = 400 ohm, Vgs = -2V
- R1 = 1k, Vgs = -3.2V
- R1 = 2k, Vgs = - 3.6V
In each case the output side of the divider should be about 0.5V. I've only roughly calculated the Vgs's since I don't know the model parameters.
The way you have the Vbias isn't 100% correct there should be a 1M resistor between the gates and Vbias.
In the real circuit the output of the LFO passes through the 3M9 (R3) then to the gates.
The bias circuit looks like a voltage source in series with a 1M resistor.
The 1M resistor allows JFETS to be biased and also allows the LFO voltage to pass to the JFETS.
The voltage swing on the LFO cap is say 1.3V p-p. When the LFO output passes through the 3M9 it is shunted to Vbias
vias 1M resistor. The 3M9 and the 1M form a voltage divider, so the 1.3Vp-p swing on the cap is reduced to 0.27Vp-p to the gates.
(Only rough numbers here.)
> 3M9
You can save zeros with "3.9Meg". (Because naked "m" is Milli.)
I'm not sure why I care how much margin to oscillate the voltage in the oscillator. In this case we would like to sweep the FET channel from >24k to a few hundred ohms. As said, this often needs trim of idle bias and sweep.
Quote> 3M9
You can save zeros with "3.9Meg".
For the OP, that's a peculiarity of spice
Quote(Because naked "m" is Milli.)
Spice is a pain for that. It originates because the original spice was as all capitals and then later it became case independent and m becomes M
When you type 3.9M in LT spice actually forces it back to 3.9m which forces clarity to the meaning.
LT spice also has an option for 3k9 format but for MEG you have to write 3MEG9 which doesn't help the cause :icon_eek:
I always keep this option off since it creates habit problems when you move to other spice versions.
Quote from: savethewhales on September 05, 2020, 11:17:12 PM
... which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.
This makes absolutely no sense.
Frederico, check out these sims I posted a while back // they show a P90 LFO swing of around 290mvpp ...
https://www.diystompboxes.com/smfforum/index.php?topic=116338.0 (https://www.diystompboxes.com/smfforum/index.php?topic=116338.0)
Quote from: Rob Strand on September 06, 2020, 12:27:57 AM
If you doubt the JFET is working you need to verify the JFET model.
Set-up an AC input voltage of 1V driving a voltage divider with a single resistor, JFET from divider output to ground, and set the gate voltage to a known value.
Roughy,
- R1 = 200 ohm, Vgs = 0V
- R1 = 400 ohm, Vgs = -2V
- R1 = 1k, Vgs = -3.2V
- R1 = 2k, Vgs = - 3.6V
In each case the output side of the divider should be about 0.5V. I've only roughly calculated the Vgs's since I don't know the model parameters.
The way you have the Vbias isn't 100% correct there should be a 1M resistor between the gates and Vbias.
In the real circuit the output of the LFO passes through the 3M9 (R3) then to the gates.
The bias circuit looks like a voltage source in series with a 1M resistor.
The 1M resistor allows JFETS to be biased and also allows the LFO voltage to pass to the JFETS.
The voltage swing on the LFO cap is say 1.3V p-p. When the LFO output passes through the 3M9 it is shunted to Vbias
vias 1M resistor. The 3M9 and the 1M form a voltage divider, so the 1.3Vp-p swing on the cap is reduced to 0.27Vp-p to the gates.
(Only rough numbers here.)
Hello Rob! Thank you for your response!
By doing what you said, like the following image:
(https://i.postimg.cc/56bBjSpn/texte.png) (https://postimg.cc/56bBjSpn)
I am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.
About the part of the 3M9 and the 1M resistors, I didn't use because I wanted to do the tests manually, that's why I didn't make all the refinements of the schematic. I can't seem to know how to simulate a real time frequency analyser on LTSpice, that's why I wanted to change the filters ground resistance "manually".
Anyway, I did the testing with the 1M resistor just like the schematic:
(https://i.postimg.cc/xJ3Y6QHr/texte2.png) (https://postimg.cc/xJ3Y6QHr)
But I got no better result (at 1.5 Volt of bias, the second cancelled frequency exceeds 20k already, just like it was before).
Also, in the LFO testings I made:
(https://i.postimg.cc/n9fjDnJ6/texte3.png) (https://postimg.cc/n9fjDnJ6)
We can see that the LFO Span is 1,6 Volt p-p (exact schematic of the phase 90 but the potentiometer is substituted by a "low resistance" of 10k), which is also different than 1,3 Volt p-p as you mentioned.
However besides all that I don't believe the LFO has anything to do with the "JFET volt span", because no matter what the LFO does, if the JFET changes resistance really drastically as i'm seeing it does (the one i'm using), it can't be used for more than 0.3 Vpp of LFO span anyway, so I'm guessing it depends most on the JFET case now.
I'm kinda lost but starting to understand more, so thank you.
Regards, Fred
Quote from: PRR on September 06, 2020, 01:30:27 AM
> 3M9
You can save zeros with "3.9Meg". (Because naked "m" is Milli.)
I'm not sure why I care how much margin to oscillate the voltage in the oscillator. In this case we would like to sweep the FET channel from >24k to a few hundred ohms. As said, this often needs trim of idle bias and sweep.
Yeah I already noticed that meg in place of the M. but either way, what you mean by "this often needs trim of idle bias and sweep."?
Isn't it kinda obvious that we need to bias the voltage that goes to the gate of the FET?
Quote from: Eb7+9 on September 06, 2020, 03:13:22 AM
Quote from: savethewhales on September 05, 2020, 11:17:12 PM
... which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.
This makes absolutely no sense.
Frederico, check out these sims I posted a while back // they show a P90 LFO swing of around 290mvpp ...
https://www.diystompboxes.com/smfforum/index.php?topic=116338.0 (https://www.diystompboxes.com/smfforum/index.php?topic=116338.0)
Eb7+9, beautiful chord it is your name.
I have the same question for you than for Rob Strand. In this case I guess the most important thing is that the JFET's itself have few span of voltage. In this matter, even if I could get a LFO with a very good voltage span, it would suit me because these specific FET's that I am simulating, don't respond well to more than 1.4 Vbias (which in practie means -3.7 VGScutoff upwards, knowing that in Spice the FET's I used are said to have cutoff at -4 VGS).
Anyway thank you very much for the information (I already saw the whole post and it will help me for sure).
Regards, Fred
Fred, you can't do large-signal (DC and Tran) sims at the origin because the models only cover one quadrant ... that's why we don't ever see jFET VCR sims done despite being an obvious thing to try in a simulator ... I would expect small-signal (AC, noise, etc ...) sim output to be bogus in values despite the control range being respected, but that depends on how the simulator would calculate the derivative at the origin exactly in an AC sim ...
Quote from: Eb7+9 on September 06, 2020, 04:59:19 PM
Fred, you can't do large-signal (DC and Tran) sims at the origin because the models only cover one quadrant ... that's why we don't ever see jFET VCR sims done despite being an obvious thing to try in a simulator ... I would expect small-signal (AC, noise, etc ...) sim output to be bogus in values despite the control range being respected, but that depends on how the simulator would calculate the derivative at the origin exactly in an AC sim ...
Hey Eb, yeah, thanks you very much for the explanation.. You guys nail it, i'm just new to some things. And it seems totally correct, all your explanation.
But that refers to the work of the JFET's (the output moving in real time), right?
That being the case, how can I simulate things of a phaser, just to be more clarified? I have to change the resistances manually, as i'm doing, right?
And what about that story of the 0.3 Vpp span of the JFET's? What should I be doing, you think?
Thanks, Fred
QuoteI am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.
Your V2 voltage needs to be negative in that test set-up.
In the phaser the JFET source is at Vref and the gate is a Vbias which is lower than Vref, which makes Vgs negative.
I don't know what JFET model you are using but LTSpice has two models and one of them looks wrong.
The 2N5486 data sheet shows,
https://www.onsemi.com/pub/Collateral/2N5486-D.PDF
VP = -4V
Yfs = 6000uS
Idss = 12mA ( consistent with VP and Yfs)
But LT spice library has *two* models,
.MODEL J2N5486 NJF(Beta=736.9u Betatce=-500m Rd=1 Rs=1 Lambda=9.5m Vto=-3.889 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=362.2m Pb=1 Fc=500m Cgs=2.414p Kf=5.497e-003f Af=1)
and
.model 2N5486 NJF(Is=.25p Alpha=1e-4 Vk=80 Vto=-4.0 Vtotc=-3m Beta=4.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17 mfg=Siliconix)
The Beta for the J2N5486 looks OK. The Beta for the 2N5486 is way too high. It implies a Yfs of 32000uS. Which is more like a switching JFET.
High Yfs like that is going to make the JFET look like a low resistance and it won't be much good for a phaser.
So when I use the J2N5486 model I get an output voltage range of 514mV to 516mV. Quite close to the expected 500mV. (I made a few tweaks to the Vgs values since I can see the model parameters: Vgs = 0V, -2.28V, -3.25V, -3.58V.)
For the 2N5486 model I get output voltages of 175mV and 225mV, clearly too low due the low JFET resistance caused by the crapaphonic model.
FWIW, here's the whole sim with accurate values (and even better agreement).
[Click to Enlarge]
(https://i.postimg.cc/zb3yRqQM/LTspice-J2-N5486-Verify-2020-09-07.png) (https://postimg.cc/zb3yRqQM)
Quote from: Rob Strand on September 06, 2020, 06:49:41 PM
QuoteI am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.
Your V2 voltage needs to be negative in that test set-up.
In the phaser the JFET source is at Vref and the gate is a Vbias which is lower than Vref, which makes Vgs negative.
Ohh yeah, of course Rob, I was naive!
As I'm doing the simulation with the source inverted, I'm not getting 0.5 V in the output side :\, on the image below I show what I got (2k resistor):
(https://i.postimg.cc/XBfyv1Xc/texttt.png) (https://postimg.cc/XBfyv1Xc)
Quote from: Rob Strand on September 06, 2020, 09:15:05 PM
I don't know what JFET model you are using but LTSpice has two models and one of them looks wrong.
The 2N5486 data sheet shows,
https://www.onsemi.com/pub/Collateral/2N5486-D.PDF
VP = -4V
Yfs = 6000uS
Idss = 12mA ( consistent with VP and Yfs)
But LT spice library has *two* models,
.MODEL J2N5486 NJF(Beta=736.9u Betatce=-500m Rd=1 Rs=1 Lambda=9.5m Vto=-3.889 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=362.2m Pb=1 Fc=500m Cgs=2.414p Kf=5.497e-003f Af=1)
and
.model 2N5486 NJF(Is=.25p Alpha=1e-4 Vk=80 Vto=-4.0 Vtotc=-3m Beta=4.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17 mfg=Siliconix)
The Beta for the J2N5486 looks OK. The Beta for the 2N5486 is way too high. It implies a Yfs of 32000uS. Which is more like a switching JFET.
High Yfs like that is going to make the JFET look like a low resistance and it won't be much good for a phaser.
So when I use the J2N5486 model I get an output voltage range of 514mV to 516mV. Quite close to the expected 500mV. (I made a few tweaks to the Vgs values since I can see the model parameters: Vgs = 0V, -2.28V, -3.25V, -3.58V.)
For the 2N5486 model I get output voltages of 175mV and 225mV, clearly too low due the low JFET resistance caused by the crapaphonic model.
Rob, now I saw this one. Thank you so much, really. I actually was using the JFET that was present in my LTSpice, I didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.
I did the simulation with the "new model" with the following circuit and parameters:
(https://i.postimg.cc/6TnHR9vz/texteeee.png) (https://postimg.cc/6TnHR9vz)
And I got 644 mV to 153 mV depending on the resistor value I tested...
Now when using it in the phaser, it responds waaay better!! I have a voltage span of 1.8 Volt now!! The only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?
**UPDATE** When I put a higher input, it gives me more gain, like ?!?!? Does that make any sense? For me no actually
Greetings, Fred
QuoteI didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.
I did the simulation with the "new model" with the following circuit and parameters:
You were using model just that the model is in the LTSpice's library. You should find the file of JFET models,
{your LTSPICE folder}\lib\cmp\standard.jft
You can open that file up as text and see the models. You can also add models.
You should be able to just change the part name on the schematic from 2N5486 to J2N5486, as you have already done, without putting the model down on the schematic. However, the models supplied in LT spice seem to vary from version to version so if your sim barfs then you might actually *need* to plop the model down on the schematic.
QuoteThe only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?
Changing the JFET shouldn't affect the gain. Maybe the DC biasing has got screwed up somewhere.
After a simulation, click on the schematic area, then move the cursor over the circuit wires. At the bottom of the LTspice window you should be able to see some numbers showing the DC voltages. Make sure they all look OK: about Vcc/2 on the opamps. check the transistor as well, the collector should sit at about 2.5V.
Quote from: Rob Strand on September 07, 2020, 06:12:25 PM
QuoteI didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.
I did the simulation with the "new model" with the following circuit and parameters:
You were using model just that the model is in the LTSpice's library. You should find the file of JFET models,
{your LTSPICE folder}\lib\cmp\standard.jft
You can open that file up as text and see the models. You can also add models.
You should be able to just change the part name on the schematic from 2N5486 to J2N5486, as you have already done, without putting the model down on the schematic. However, the models supplied in LT spice seem to vary from version to version so if your sim barfs then you might actually *need* to plot the model down on the schematic.
QuoteThe only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?
Changing the JFET shouldn't affect the gain. Maybe the DC biasing has got screwed up somewhere.
After a simulation, click on the schematic area, then move the cursor over the circuit wires. At the bottom of the LTspice window you should be able to see some numbers showing the DC voltages. Make sure they all look OK: about Vcc/2 on the opamps. check the transistor as well, the collector should sit at about 2.5V.
Hi Rob,
You are helping me a ton, really. I just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!
Unhappily, the collector gives 3.27 V DC, for some reason. The op-amp gives 9V in the positive and 0 V in the negative, as i'm using a 9V baterry to power up.
Greetings, Fred
QuoteI just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!
OK cool.
QuoteUnhappily, the collector gives 3.27 V DC, for some reason.
That's not enough to cause the -14dB.
A small detail is the Vref is actually about 4.8V on the real circuit. Even though the zener is 5.1V, the zener is operating at a low current and that causes the zener voltage to drop to 4.8V. If you make that change it will drop the collector voltage down to 2.97V.
The difference from 2.5 to 2.9V could be caused by the model [the reason is the transistor is operating at low current so the Vbe is 0.59V not the assumed 0.65V.] I can't remember the exact voltage on the real unit.
I think the real problem is your signal source is 0.1V AC. dB in spice is referenced to 1V so you are only putting in a -20dBV signal. The summing from the mixer will give 6dB gain so that adds up to -14dBV. In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.
All you need to change is your AC voltage, make it 1V. FWIW, the AC voltage levels won't cause any clipping in spice. It's a small-signal mode. You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V. All the AC level does is change the scaling of the numbers. For eyeballing gains a 1V AC input is by far the most convenient number. When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.
Quote from: Rob Strand on September 07, 2020, 07:19:32 PM
QuoteI just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!
OK cool.
QuoteUnhappily, the collector gives 3.27 V DC, for some reason.
That's not enough to cause the -14dB.
A small detail is the Vref is actually about 4.8V on the real circuit. Even though the zener is 5.1V, the zener is operating at a low current and that causes the zener voltage to drop to 4.8V. If you make that change it will drop the collector voltage down to 2.97V.
The difference from 2.5 to 2.9V could be caused by the model [the reason is the transistor is operating at low current so the Vbe is 0.59V not the assumed 0.65V.] I can't remember the exact voltage on the real unit.
I think the real problem is your signal source is 0.1V AC. dB in spice is referenced to 1V so you are only putting in a -20dBV signal. The summing from the mixer will give 6dB gain so that adds up to -14dBV. In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.
All you need to change is your AC voltage, make it 1V. FWIW, the AC voltage levels won't cause any clipping in spice. It's a small-signal mode. You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V. All the AC level does is change the scaling of the numbers. For eyeballing gains a 1V AC input is by far the most convenient number. When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.
It's reasonable that those changes might be for the low current and the model/components used. I just fear that the simulations might be too diferrent in real life, that would actually suck.
Quote from: Rob Strand on September 07, 2020, 07:19:32 PM
I think the real problem is your signal source is 0.1V AC. dB in spice is referenced to 1V so you are only putting in a -20dBV signal. The summing from the mixer will give 6dB gain so that adds up to -14dBV. In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.
So, as I mentined before, I was just testing the voltages on the input, and as a standar I was actually using 1Volt so you're right. It gives a bettwr result. It's just it shouldn't be different response fpr diferrent input voltages, I guess. Why would I have more gain on higher voltages?
Quote from: Rob Strand on September 07, 2020, 07:19:32 PM
All you need to change is your AC voltage, make it 1V. FWIW, the AC voltage levels won't cause any clipping in spice. It's a small-signal mode. You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V. All the AC level does is change the scaling of the numbers. For eyeballing gains a 1V AC input is by far the most convenient number. When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.
I did 1V and got +- 5dB of gain in the end of the chain. And thanks for the insight on the working of the simulations. That could help me a ton. I actually had problems one time with amplitude response (on 3 different softwares I couldn't do it with an class AB amplifier if I'm not mistaken, and my colleagues too).
Anyway, with a voltage divider I must be able to have 0 gain on the output, right? Or do you recommend me trying only when I test it physically?
Greetings, Fred
QuoteIt's reasonable that those changes might be for the low current and the model/components used. I just fear that the simulations might be too diferrent in real life, that would actually suck.
The low current thing is a real effect. For transistors the spice models are quite good and can represent real life. However just like you found with the two JFET models, the spice model for a given part might not be trustworthy unless you verify it - which takes extra effort.
For the zener the low voltage a low currents is a known characteristic of zeners. People have measured the voltage on the MXR pedals over the years and it does come out around 4.8V.
There's no zener model in spice and zener models are the least trustworthy. Many won't show enough drop in voltage at low currents.
If you take your simulation you have a solid Vbias. Physically that's not realistic but it's often a good strategy. To make the simulation better you would use the human knowledge that the zener voltage is 4.8V and not the 5.1V on the label. The simulation would represent reality quite well and you don't have to deal with the messy problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!
In general you have to have a good level of mistrust in spice. The models are rarely good. Different models from different manufacturers vary. I've got about 5 models for LM741 opamps and only one or two are even close to reality. For AC simulations, I don't even use real models I use something like LTspice's model "opamp"; IIRC the supplied model had a bug. For .TRANS you need on opamp model with PSU rails.
Quote
So, as I mentined before, I was just testing the voltages on the input, and as a standar I was actually using 1Volt so you're right. It gives a bettwr result. It's just it shouldn't be different response fpr diferrent input voltages, I guess. Why would I have more gain on higher voltages?
The key thing is it doesn't plot gain. It plots dBV, which is defined as
dbV = 20*log10( V / 1V) = 20*log10(V)
It is simply a conversion of volts to dB without any consideration of the input source level.
For gain you need,
dB gain = 20*log10(Vout/Vin).
So the two only agree when Vin is 1V.
You can actually plot expressions in LTspice and other Spice versions, so if you wanted you could plot the AC analysis expression,
Vout/Vin
and then plot would show dB gain = 20*log10(Vout/Vin).
In some versions of spice the variable expressions are already in dB and to get gain you can type something like Vout - Vin, which is actually dB(Vout) - dB(Vin).
Quote
I did 1V and got +- 5dB of gain in the end of the chain. And thanks for the insight on the working of the simulations. That could help me a ton. I actually had problems one time with amplitude response (on 3 different softwares I couldn't do it with an class AB amplifier if I'm not mistaken, and my colleagues too).
Unfortunately with spice sims it only takes one thing to go wrong and it all falls in a heap; like not plugging in the power on your breadboard. Small differences between packages can confuse things. I often start with simple dumb circuits where you already know the answer, then run a lot of sims and play with the waveform plotter. No doubt you will find some things which don't make sense. Good to keep notes.
Quote
Anyway, with a voltage divider I must be able to have 0 gain on the output, right? Or do you recommend me trying only when I test it physically?
I'm not sure what you are asking here.
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM...the zener voltage is 4.8V and not the 5.1V on the label. ... problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!
Yes, don't trust SPICE at all, or its models.
The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.
Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.
(https://i.postimg.cc/xcr9QPQs/1-N750-plot-42.gif) (https://postimg.cc/xcr9QPQs)
QuoteCurious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.
The MXR is nominally 5.1V (so perhaps a 1N751 is more the shot ) and ends up at 4.8V @ 420uA.
So some very crude scaling for the 4.7V 1N750 would be 4.8 * (4.7 / 5.1) = 4.4V @ 420uA.
Your sim shows the model at 4.1V to 4.2V so not too bad.
But yes for > 7V or so the knees are on the spice models are probably a bit softer than a real zener.
Of hand the one in this thread is the Motorola/On-semi model and think they only use BV which is the sloppy model.
Some manufacturers have more elaborate sub-circuits.
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
The low current thing is a real effect. For transistors the spice models are quite good and can represent real life. However just like you found with the two JFET models, the spice model for a given part might not be trustworthy unless you verify it - which takes extra effort.
Yeah, I wouldn't want to take that "effort" because I actually want to build the pedal, so no spare time.
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
For the zener the low voltage a low currents is a known characteristic of zeners. People have measured the voltage on the MXR pedals over the years and it does come out around 4.8V.
There's no zener model in spice and zener models are the least trustworthy. Many won't show enough drop in voltage at low currents.
I will actually assume 4,8 V then (I will have to trust you and mr. PRR), cause I understand that it doesn't do as well as we imagine, never, and it makes sense that at a low current, there's less voltage drop.
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
If you take your simulation you have a solid Vbias. Physically that's not realistic but it's often a good strategy. To make the simulation better you would use the human knowledge that the zener voltage is 4.8V and not the 5.1V on the label. The simulation would represent reality quite well and you don't have to deal with the messy problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!
In general you have to have a good level of mistrust in spice. The models are rarely good. Different models from different manufacturers vary. I've got about 5 models for LM741 opamps and only one or two are even close to reality. For AC simulations, I don't even use real models I use something like LTspice's model "opamp"; IIRC the supplied model had a bug. For .TRANS you need on opamp model with PSU rails.
Yeah, I'm going to do that, or at the worst case, try to simulate with the LTSpice zener model with modified values for what I want (like 5.1 V/ 4.8 V etc).
I'm getting to know better Spice and assume that it's kinda getting on my nerves. But I will keep the information you are telling me for the future.
One thing I would ask is if there's any better/reliable/free software for simulation than Spice (maybe MultiSim?)?
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
The key thing is it doesn't plot gain. It plots dBV, which is defined as
dbV = 20*log10( V / 1V) = 20*log10(V)
It is simply a conversion of volts to dB without any consideration of the input source level.
For gain you need,
dB gain = 20*log10(Vout/Vin).
So the two only agree when Vin is 1V.
You can actually plot expressions in LTspice and other Spice versions, so if you wanted you could plot the AC analysis expression,
Vout/Vin
and then plot would show dB gain = 20*log10(Vout/Vin).
In some versions of spice the variable expressions are already in dB and to get gain you can type something like Vout - Vin, which is actually dB(Vout) - dB(Vin).
I know what is dBV and dBu etc, cause I actually learned it at college, and that's really why I thought it was strange that those results were given to me as dB in software. In this matter, I didn't understand well how I can get "the real" dB in Spice. Maybe doing that dB(Vout)-dB(Vin) as you said, is that it? If so, where do I write the expression?
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
Unfortunately with spice sims it only takes one thing to go wrong and it all falls in a heap; like not plugging in the power on your breadboard. Small differences between packages can confuse things. I often start with simple dumb circuits where you already know the answer, then run a lot of sims and play with the waveform plotter. No doubt you will find some things which don't make sense. Good to keep notes.
For my case, I already knew what was supposed to come out of the circuit (out of the phase shifting part) but of course if I wanted to "test" a component (like I ended up doing on the JFET) I would have to do simple circuits and see through my own eyes how it responded.
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM
I'm not sure what you are asking here.
Better forget it, neither I do, as I'm looking back.
Quote from: PRR on September 08, 2020, 09:43:21 PM
Yes, don't trust SPICE at all, or its models.
The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.
Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.
(https://i.postimg.cc/xcr9QPQs/1-N750-plot-42.gif) (https://postimg.cc/xcr9QPQs)
Yeah, that of the Zener current makes all sense.
It's actually impressive what you plotted there. Pretty curious how the Zener diode operates under lower currents. In this case, the plot is of the only zener that there is on Spice right? And did you put that Bv yourself or does it come like that? Another thing is where is the 10k? Are you refering to the current that goes to the zener on the schematic of the P90? Or smth else?
Would you reccomend me using another way to have a reference voltage, or the Zener would serve me well, for the likes of the P90 schematic? Because the maximum that will happen is that I will not have as linear a frequency sweep on the output as I would want if I use a Zener and it changes voltage too much, I guess.
Quote from: Rob Strand on September 08, 2020, 10:56:47 PM
The MXR is nominally 5.1V (so perhaps a 1N751 is more the shot ) and ends up at 4.8V @ 420uA.
So some very crude scaling for the 4.7V 1N750 would be 4.8 * (4.7 / 5.1) = 4.4V @ 420uA.
Your sim shows the model at 4.1V to 4.2V so not too bad.
But yes for > 7V or so the knees are on the spice models are probably a bit softer than a real zener.
Of hand the one in this thread is the Motorola/On-semi model and think they only use BV which is the sloppy model.
Some manufacturers have more elaborate sub-circuits.
Funny thing is I bought this one: https://www.musikding.de/Zener-51V-05W_1 and I'm already predicting it's not very accurate for sure.
I understand where you're trying to get, but where did this expression came from: 4.8 * (4.7 / 5.1) = 4.4V @ 420uA ?
Quote
I'm getting to know better Spice and assume that it's kinda getting on my nerves. But I will keep the information you are telling me for the future.
One thing I would ask is if there's any better/reliable/free software for simulation than Spice (maybe MultiSim?)?
Most simulators are basically spice. Spice mostly works. The root of the problems that come up are quite technical and there's multiple layers to the causes.
Spice is just a big calculator. Each type of device is based on a mathematical model of the device, for example there is a mathematical model for a diode. The mathematical model has parameters which are different for each part, for example the parameters for a 1N4004 diode are different to the parameters for a 1N4148 diode.
So the problems,
1) The parameters in the model don't represent reality. I'd say this is the biggest problem in spice.
As you can imagine this will happen on any package. For example you have a 1N4148 diode model but in spice the behavior doesn't match the real part. This is exactly the problem you had with the JFET. There's not much you can do. Try another model or tweak the parameters yourself. What I do is verify models just like I verified the JFET and found the problem. After that I make notes explaining which models are bad and which are good. In the end you create you own set of verified models. These are the models you know work.
2) The parameters are sort of correct. The model works at say 1mA but it doesn't work at 10uA. This is common as well.
There are two causes:
2a) the spice parameters for the part are only partially correct. Whoever created the model didn't match the full behaviour
of the device. This one is pretty common as well.
The fix is to try another model, one from a different source or manufacturer.
2b) The mathematical model in spice isn't good enough to cover a wide range of operating conditions.
So this is like the zener case. You can tweak the parameter to be roughly right in one region, say Iz=20mA,
but when you look at 20uA it is way off. You get similar problems with MOSFETs as well.
Not much you can do. In some cases I have two models one for high-currents and one for low currents.
One way people deal with case 2b is to come up with a macro model. This is a whole circuit which better models the part.
https://www.onsemi.com/pub/Collateral/AND8250-D.PDF
In theory this is OK but the problem with these models is: they are not available for many parts. You have to work out the
parameters from the datasheet or from measurements. Because model is more complex you have a lot more parameters to
tune-up. Most people that do this use numerical optimization software to choose the parameters based on a least squares fit.
Way beyond what most people do.
The next step up from the macro model is to come-up with better sets of equations that represent the parts. You will see this in research papers. The only way you will get those equations into spice is with a complex macro model, or re-compile the spice engine with a new model. Also, you it has the same problem as the macro model that you have a heap of parameters to tune-up.
QuoteI didn't understand well how I can get "the real" dB in Spice. Maybe doing that dB(Vout)-dB(Vin) as you said, is that it? If so, where do I write the expression?
Don't use the dB()-dB() thing in LTSpice, that only makes sense in *some* *other* spice programs. In LTspice you would type, V(Vout)/V(Vin) where Vout and Vin are labels you have added. The *waveform viewer* will convert the linear variables to dB.
To add expressions right click on the plotted variable that appears at the top of the Waveform Viewer window; you need to have plotted something already. The change what is displayed by typing in an expression.
Quote
For my case, I already knew what was supposed to come out of the circuit
You pretty much have to be on your guard all the time. If you trust your models and you know what silly mistakes you do then it's a lot easier to pick up problems. I've used spice for about 35 years and there's plenty of stuff I trust 99%. I don't even bother doing hand calculations because I know spice will do the same darn thing with no effort. However, if I grab an unverified model for a part I don't trust it at all. That's especially true for IC models. For things like diodes, transistors and jfets I might choose not to use a model from the web which matches the part number, I'll use one of my trusted models which is close first.
Quote
I understand where you're trying to get, but where did this expression came from: 4.8 * (4.7 / 5.1) = 4.4V @ 420uA ?
If we know the 5.1V zener is 4.8V at 420uA then we know the voltage drops by a factor of 4.8/5.1.
So if we assume the 4.7 zener drops roughly by the same factor at low currents, we expect it to be 4.7 * (4.8/5.1) = 4.4V @ 420uA as least to ball-park accuracy. I wouldn't be confident applying the factor to a 9.1V zener as they will not behave like a 5.1V zener.
> if there's any better/reliable/free software for simulation than Spice (maybe MultiSim?)?
SPICE is a black box.
https://en.wikipedia.org/wiki/SPICE
http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/
I *have* piped hand-typed text files to SPICE, a very long time ago. What everybody uses is a "spice package" such as Orcad/Pspice, NGspice, LTspice, Tina-TI, NL5, Cadence, Proteus, MultiSim, SIMetrix, Beige Bag, Electronic Workbench............. generally a bundle of schematic input, test parameters, pre- and post-processing and viewing, with at least a starter pile of parts (models).
> where is the 10k? Are you refering to the current that goes to the zener on the schematic of the P90?
It is generally as easy to solve for "ALL cases" as for the "P90 case". I swept the zener voltage around the nominal voltage and plotted the current. Now I have a reference, not just for 9V 10k, but for 50V 2k 300V 300k etc.
It might be clearer, in retrospect, to sweep current from 1uA to 100mA. I know zeners and know it make no difference; some other parts/systems it might.
One thing which is interesting is the spec for the 1N750 says the slope is Zd = 19 ohms @ 20mA but the simulation is about 3 ohms @ 20mA. If you look at the1N5230B datasheet it quotes the same value, and in addition a Zd value at a lower current.
If you imagine modifying the curve to change the slope (actually 1/slope) from 3 ohms to 19 ohm it's a big change in slope. It hardly seems possible to get that slope to pass through 4.4V @ 420uA - even as a curve drawing exercise, never mind a model. I did a simple change to the model to match Zd = 19 ohms @ 20mA and it hits 10mA @ 4.4V.
(https://i.postimg.cc/S2dkJYrT/1-N750-4-V7-500m-W-2020-09-11.png) (https://postimg.cc/S2dkJYrT)
FWIW the 19 ohm could the maximum although it does not say so in the datasheet.
Quote from: Rob Strand on September 09, 2020, 11:09:27 PM
Most simulators are basically spice. Spice mostly works. The root of the problems that come up are quite technical and there's multiple layers to the causes.
Spice is just a big calculator. Each type of device is based on a mathematical model of the device, for example there is a mathematical model for a diode. The mathematical model has parameters which are different for each part, for example the parameters for a 1N4004 diode are different to the parameters for a 1N4148 diode.
Yeah, I even got problems with literally the 1N4148 if I'm not mistaken hahahah (or smth involved with amplifiers).
That of writing down what is right/wrong could help a ton. I just don't feel the need right now because I'm realising the other JFET model you sent me works fine.
Quote
In some cases I have two models one for high-currents and one for low currents.
This is really smart. I'll start doing that when I need it. The part where I don't know yet is changing the parameters myself, which I would kindly ask you to teach me if you'd be able to.
Quote
One way people deal with case 2b is to come up with a macro model. This is a whole circuit which better models the part.
https://www.onsemi.com/pub/Collateral/AND8250-D.PDF
Super interesting. I'll check on that when I can. It seems really hard to get this right, but in theory seems what's correct, as the components are never linear.
Quote
Don't use the dB()-dB() thing in LTSpice, that only makes sense in *some* *other* spice programs. In LTspice you would type, V(Vout)/V(Vin) where Vout and Vin are labels you have added. The *waveform viewer* will convert the linear variables to dB.
To add expressions right click on the plotted variable that appears at the top of the Waveform Viewer window; you need to have plotted something already. The change what is displayed by typing in an expression.
Ok now this helped me a lot. I get the actual gain of the circuit. It's 5 dB no matter what voltage I put, which makes total sense (the why's will come later).
Quote
You pretty much have to be on your guard all the time. If you trust your models and you know what silly mistakes you do then it's a lot easier to pick up problems. I've used spice for about 35 years and there's plenty of stuff I trust 99%. I don't even bother doing hand calculations because I know spice will do the same darn thing with no effort. However, if I grab an unverified model for a part I don't trust it at all. That's especially true for IC models. For things like diodes, transistors and jfets I might choose not to use a model from the web which matches the part number, I'll use one of my trusted models which is close first.
Wow 35 years it's a heck of a long time on this soft. How do you know when a Model is verified? I'd like to learn that, and to be able to change my models to what I want, but that's what I asked above hahah.
Quote
If we know the 5.1V zener is 4.8V at 420uA then we know the voltage drops by a factor of 4.8/5.1.
So if we assume the 4.7 zener drops roughly by the same factor at low currents, we expect it to be 4.7 * (4.8/5.1) = 4.4V @ 420uA as least to ball-park accuracy. I wouldn't be confident applying the factor to a 9.1V zener as they will not behave like a 5.1V zener.
Wow this is smth else, I don't think I got it but I got it at the same time. I'd have to do simulations to see with my own eyes (don't think I'm doubting.. I won't forget what you're saying here.)
One thing, I just received my shipment of components, and I ordered a matched set of 4 FET's, which (as I did the JFET VGS R.G. Keen's test) are matched at around -0.7 V (2x -0.7 and 2x -0.67). That didn't seem to satisfy me, and at the same time this didn't surprise me. Does anyone think these too low values and this 5% difference will make a big deal on the phaser? I'm just thinking a 0.7 Volt sweep (or less) on the LFO might be too low (I would have to change the integrating time I guess).
Quote from: PRR on September 10, 2020, 04:12:12 PM
SPICE is a black box.
https://en.wikipedia.org/wiki/SPICE
http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/
I *have* piped hand-typed text files to SPICE, a very long time ago. What everybody uses is a "spice package" such as Orcad/Pspice, NGspice, LTspice, Tina-TI, NL5, Cadence, Proteus, MultiSim, SIMetrix, Beige Bag, Electronic Workbench............. generally a bundle of schematic input, test parameters, pre- and post-processing and viewing, with at least a starter pile of parts (models).
Okk, understood... So for what I'm seeing, I must choose the best user interface for me and I should be good to go, right?
Quote
It is generally as easy to solve for "ALL cases" as for the "P90 case". I swept the zener voltage around the nominal voltage and plotted the current. Now I have a reference, not just for 9V 10k, but for 50V 2k 300V 300k etc.
It might be clearer, in retrospect, to sweep current from 1uA to 100mA. I know zeners and know it make no difference; some other parts/systems it might.
Okk nice! I will do the simulation myself too, it's good for me to understand (and put on my project maybe hahah).
Quote from: Rob Strand on September 11, 2020, 02:05:57 AM
One thing which is interesting is the spec for the 1N750 says the slope is Zd = 19 ohms @ 20mA but the simulation is about 3 ohms @ 20mA. If you look at the1N5230B datasheet it quotes the same value, and in addition a Zd value at a lower current.
If you imagine modifying the curve to change the slope (actually 1/slope) from 3 ohms to 19 ohm it's a big change in slope. It hardly seems possible to get that slope to pass through 4.4V @ 420uA - even as a curve drawing exercise, never mind a model. I did a simple change to the model to match Zd = 19 ohms @ 20mA and it hits 10mA @ 4.4V.
(https://i.postimg.cc/S2dkJYrT/1-N750-4-V7-500m-W-2020-09-11.png) (https://postimg.cc/S2dkJYrT)
FWIW the 19 ohm could the maximum although it does not say so in the datasheet.
I would like to know this kind of simulation.. I will give it a try and give feedback here. Cause I'm not understanding much, what I get is that you can prove that the simulation doesn't reflect real life in this case.
Another thing is the impedance which you refer , how do you calculate it? It's not only Voltage/Current in this case , right? Like if the voltage is 4.7 V and the current is 20mA, shouldn't the impedance be 235 ohm? hahhahah
Quote from: PRR on September 08, 2020, 09:43:21 PM
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM...the zener voltage is 4.8V and not the 5.1V on the label. ... problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!
Yes, don't trust SPICE at all, or its models.
The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.
Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.
(https://i.postimg.cc/xcr9QPQs/1-N750-plot-42.gif) (https://postimg.cc/xcr9QPQs)
PRR, regarding this post, how do I plot current? Because when I add traces I can't seem to find the right current, there's only current in the Zener diode and current of the source...
(https://i.postimg.cc/5Q85PSRN/zener-plot-try.png) (https://postimg.cc/5Q85PSRN)
QuoteThe part where I don't know yet is changing the parameters myself, which I would kindly ask you to teach me if you'd be able to.
It's largely a mathematical game. You have to know the relationship between measurements or datasheet specs and the spice parameters. It's helps to pull-up the equations spice uses and to know the equations for the "basic theory" of a device. Some things are easy but on the whole it's quite difficult and you need to pull on a lot of knowledge. Much easier is to try a few models form other sources or manufacturers and just try them. (It's very much like software development, if the library you downloaded doesn't work you can find another one or spend many hours fixing the broken one.)
QuoteIt seems really hard to get this right, but in theory seems what's correct, as the components are never linear.
There's no corrrect model yet, only OK-ish models, and small improvements. If you read the opening paragraphs of this paper, you begin to see the problem,
https://www.aeng.com/articles/Zener.pdf
Quote
One thing, I just received my shipment of components, and I ordered a matched set of 4 FET's, which (as I did the JFET VGS R.G. Keen's test) are matched at around -0.7 V (2x -0.7 and 2x -0.67).
RG's tester is fine for matching but the actual voltages you measure are always low (in magnitude). Maybe a factor of 1.5 or so (can't remember the details). If you go to section 11 here,
http://runoffgroove.com/fetzervalve.html
The resistors in the source are much higher. You need 1M ot 10M. BTW, connecting your multimeter alone can be 1M or 10M, even without the resistor in the circuit.
Quote
Ok now this helped me a lot. I get the actual gain of the circuit. It's 5 dB no matter what voltage I put, which makes total sense (the why's will come later).
That's weird. It's like the voltage used for the AC sim isn't the one you are changing. Best thing here is to probe you input voltage voltage source. Make sure it follows what you set. Are you sure you are changing the AC value? If you the DC value or the SINE magnitude it will not affect the AC simulation at all - they are all different numbers.
Quote
How do you know when a Model is verified? I'd like to learn that, and to be able to change my models to what I want, but that's what I asked above hahah.
When it matches the datasheet and/or the measurements. Also you might verify a model with DC bias points but that doesn't not verify it for frequency response. For example DC bias lets you tune the gain and Vbe of a transistor but it gives no indication of the AC performance. So you need to very under different conditions. Then neither of those will verify when the transistor is operated as a switch!
QuoteI would like to know this kind of simulation.. I will give it a try and give feedback here. Cause I'm not understanding much, what I get is that you can prove that the simulation doesn't reflect real life in this case.
The problem here is real life doesn't seem to make sense. The slope at 20mA is from datasheet. The 4.4V at 420uA is from measurements. It looks like both together can't make sense. That was my main point. When that happens I start to suspect the meaning of the the values in the datasheet. You get maximum values, minimum values and typical values. Our measurements are usually close to typical, you don't really know. However, you rarely get real devices which are at the minimum and maximum. In fact manufacturers may not even have produced them. If something went wrong they are "allowed" to ship them because they are still in spec.
I wouldn't worry to much about the example, other than it shows something isn't right. I'm starting to think the datasheet is the maximum Zd even though it doesn't actually say that.
QuoteAnother thing is the impedance which you refer , how do you calculate it? It's not only Voltage/Current in this case , right? Like if the voltage is 4.7 V and the current is 20mA, shouldn't the impedance be 235 ohm? hahhahah
It's a parameter given for Zeners. It represents how constant the voltage is when the current is varied. The resistance increases at low current, which means that zeners don't regulate well at low currents. If a zener was 4.7V at 20mA and 4.8V at 21mA then the (local) slope is (4.8-4.7)/(21mA - 20mA) = 100 ohm. That would be a zener that doesn't regulate too well. In fact if you just had a 235 ohm resistor it would produce 4.7V drop at 20mA and 4.935V ar 21mA.
Here's an example showing how RG's tester produces small Vgs measurements.
Take a 2N5485, from datasheet some representative parameters are,
VP = 2.25V
YFS0 = 5250uS
IDSS= 5.91mA (consistent with VP and YFS0)
RG's circuit tests by adjusting VGS so the drain current is such that there is 4.5V across a 10k resistor, ie.
ID_test = 4.5 / 10k = 450uA
The JFET equation is,
ID = IDSS (1+ VGS / |VP|)^2 ; VGS <= 0
The VGS value measured by RG's tester will be
450uA = 5.91mA (1+ VGS/|VP|)^2
ie.
VGS/|VP| = - 0.724
So the VGS measurement will be,
VGS_meas = = -0.724 |VP| = - |VP| / 1.38
Which is quite a bit lower than |VP|.
In this case we can get the true VP by multiplying VGS_meas by 1.38.
Unfortunately the multiplying factor depends on the actual IDSS for that specific JFET. You can't use the datasheet IDSS. You would need to measure IDSS for each JFET in order to get a correction factor for each JFET.
A correction factor of 1.4 is only good for ball-park comparisons against other testers.
The GGG tester tests at a much lower current and the measured |VGS| is much closer to |VP|. For a 10M resistor it's very close indeed.
It may not be necessary to quote-back the ENTIRE text you are responding to.
Quote from: savethewhales on September 11, 2020, 09:12:25 PM....PRR, regarding this post, how do I plot current? Because when I add traces I can't seem to find the right current, there's only current in the Zener diode and current of the source...
What other currents did you expect to find?
A single loop with no side-loops, the current is the same anywhere in the loop.
Basics like that come before fine details of crappy model approximations.
Quote
...It's largely a mathematical game... you can find another one or spend many hours fixing the broken one.)
Ok thank you very much. The thing is, do I change them in those lib folders in the Spice menu? Or elsewhere?
QuoteThere's no corrrect model yet...
https://www.aeng.com/articles/Zener.pdf
Yeah I understand that.. At least it’s better than the normal models.
I read it and it really gives life and meaning to what we were talking here in the forum…
Quote
RG's tester is fine for matching but the actual voltages... BTW, connecting your multimeter alone can be 1M or 10M, even without the resistor in the circuit.
So you’re saying they’re low, as for they’re wrong?
The resistors in the text you sent are really very big (differently from R.G's test), but I will give it a try, then.
Quote
That's weird... they are all different numbers.
I did the testiings changing the input (AC small-signal) and putting there a probe (and the gain). Here you go:
Voltages are 0.1, 0.5, 1, 2, 15 V.
(https://i.postimg.cc/qzVvDgdj/phaser-test-0-1-VAC.png) (https://postimg.cc/qzVvDgdj)
(https://i.postimg.cc/fSXTTQYc/phaser-test-0-5-VAC.png) (https://postimg.cc/fSXTTQYc)
(https://i.postimg.cc/z3RfkK4y/phaser-test-1-VAC.png) (https://postimg.cc/z3RfkK4y)
(https://i.postimg.cc/WFx1v1qp/phaser-test-2-VAC.png) (https://postimg.cc/WFx1v1qp)
(https://i.postimg.cc/ZBW52dRD/phaser-test-15-VAC.png) (https://postimg.cc/ZBW52dRD)
Quote
When it matches the datasheet and/or the measurements... Then neither of those will verify when the transistor is operated as a switch!
Alright, that’s important. But you don’t go there verifying every component you use, or do you? Like really seriuosly, if I would do that it “seems” (because it’s just a guess) that it would take a very long time.
Quote
The problem here is real life doesn't seem to make sense... I'm starting to think the datasheet is the maximum Zd even though it doesn't actually say that.
Fair enough, Just starting to understand the bullcrap regarding electronics.
Quote
It's a parameter given for Zeners... it would produce 4.7V drop at 20mA and 4.935V ar 21mA.
Nice… So it’s all about the slope then! And in the datasheet is it supposed to show the slope related to the maximum and minimum values of voltage? The slope that appears there should be related to the subtraction of the max/min I would suppose.
QuoteHere's an example showing how RG's tester produces small Vgs measurements...For a 10M resistor it's very close indeed.
Nice man! Understood, gonna do the GGG test as soon as I can. What is now pissing me is that R.G does refer to the values measured as VGSoff somewhere in the text, which is not correct…
Quote
It may not... Basics like that come before fine details of crappy model approximations.
You're right, I was quoting too much, but now I'm starting to understand this better...
It's just with the plot I would like to have reasonable results like yourself, and I didn't...
Oh and one more thing, the model approximations wasn't something I wanted to go more deep, I just wanted help to find me some model that would work, and that's what you guys helped me to. The rest of the discussion was important to me, but not mandatory.
Alright.. after writing down this message I went down and finally understood the problem. The current was inverted, of course, and I was able to plot it right doing -Id (as you did):
(https://i.postimg.cc/SJB1MFCX/currentplot-Zener1-N750-Fred.png) (https://postimg.cc/SJB1MFCX)
QuoteThe thing is, do I change them in those lib folders in the Spice menu? Or elsewhere?
The general idea is covered here,
https://adamsiembida.com/adding-spice-models-to-ltspice/
A few of things worth adding:
- you can add models to your project folder, which is only available to the project,
or, you can add them to the LTspice folders so they are available to all project.
The precise location of the folders depends on you OS, it's in the article.
- Normally you have to put a .lib or .inc on your schematic.
- You can put a heap of .models or .subckts in the one file to make a project library
or you own personal library.
- The article talks about the <system path> \lib\sub folder. There's also stuff
in the <system path> \lib\cmp folder.
- On LTspice I haven't worked out how to add you own library without adding .lib or .inc;
just as you don't need to add .lib or .inc for the "builti-in" LTspice parts
QuoteSo you're saying they're low, as for they're wrong?
QuoteWhat is now pissing me is that R.G does refer to the values measured as VGSoff somewhere in the text, which is not correct...
They are only wrong if you interpret them as VGS_off. Some people have complained about this in the past. The values produced by RG's tester are fine for matching. However, yes, calling it VGS_off does cause problems; I guess that's my only beef. The main problem is people on the group use different testers and that don't say which one they use. So when people put up their VGS measurements you have no idea how to interpret the value. If people say which tester they use then at least you can correct the values from RG's using the correction factor I calculated (or one like it).
QuoteI did the testiings changing the input (AC small-signal) and putting there a probe (and the gain). Here you go:
Voltages are 0.1, 0.5, 1, 2, 15 V.
OK I get it.
When you plot gain (Vout/Vin) you *expect* the gain to be constant with level. If you have a gain of 10 (20dB), 1V in is 10V out and 2V in is 20V out but in both cases Vout/Vin is 10 (or 20dB). The whole reason for plotting Vout/Vin was to get a gain which is independent of Vin! The other alternative, which is what I prefer, is to plot Vout and use 1V inputs. That way plotting Vout is the same as gain. However, if for some reason you want to see the output voltage for a different input you just chain it - since you changed it you don't expect to see gain anymore.
I doesn't matter which way to you do so long as you know how to interpret the results - otherwise you will be scratching your head in frustration! (And no, I'm not immune to this even after 35 years of using spice, I just do it less often.)
Quote
Alright, that's important. But you don't go there verifying every component you use, or do you? Like really seriuosly, if I would do that it "seems" (because it's just a guess) that it would take a very long time.
So the main problem is if you *never* check against reality you are just seeing numbers on the computer. They could be anything. One simple check against reality is what you expected, perhaps from rough calculations, perhaps from when you build the real unit, perhaps from experience, perhaps from common sense.
Beyond that yes it's a big job. So the idea is you use existing models, if they look wrong, find another one. If you develop a mistrust for all the models you need to check against reality. Then if you are convinced all the models suck you need to create your own.
To tell you the truth I vary rarely enter a whole circuit from the "design" schematic into spice. I use the least amount of models possible. For example a circuit might have an oscillator using a NE555 timer. I don't use the NE555 I use a spice square wave or rectangular wave. That replaces 50 parts in a possibly non-working model with one part which has to work. If I'm simulating AC response I never use opamp models ie. the ones with a power supply. For opamps I'd use something like the 'opamp' model and type-in the Gain and Bandwidth product into the parameters. For a zener I use a voltage source.
For the phaser AC response I'd probably enter most of it like you have but with the simpler opamp model. I would replace the LFO with a DC fixed DC voltage. I might simulate the LFO separately to work out the peak to peak output voltage and frequency. If I wanted the LFO I'd probably use spice voltage source to create a triangle wave.
Basically I don't *rely* on models. My simulations are probably 10 times faster than most peoples. They much easier to debug because most of it *has* to work. When you plop down a whole heap of ICs with unverified models the results are hit and miss.
Quote
Fair enough, Just starting to understand the bullcrap regarding electronics.
There's a lot of it. Some things are just technically difficult you might to know a whole book to answer one seemingly simple question. However, things like datasheets can be difficult to interpret or don't have the full enough info. It's often difficult to translate datasheet to spice models. There are programs to do this but they aren't free. There's a few sites on the web about converting datasheets to spice models
QuoteNice... So it's all about the slope then! And in the datasheet is it supposed to show the slope related to the maximum and minimum values of voltage? The slope that appears there should be related to the subtraction of the max/min I would suppose.
Slope is about how well the Zener regulate, which is kind of it's job. The slope changes at different currents. There's other issues like one manufacturer will rate their 4.7V zener at 5mA and another might rate theirs at 20mA or 43mA. As far as the datasheet goes they are incomplete from a spice model perspective, or even a from a user perspective for that matter eg. little low current info. For design we might care about worst case but for spice we might want to know typical. The datasheet have a few spare points maybe Vz + Iz or Zz (slope) vs Iz. Typical values aren't always given. The manufacturer tests against the values in the datasheet, so they will use min and max. that's all they are willing to guarantee you. If you measured 10 zeners with the same part number and the same batch you might end-up with a different view of the world, but at least one which will match the circuit you build.
A lot of parts are not precisely defined. Look at transistors (BJTs). The gain(hFE) in the datasheet is all over the map. If you measured 10 real parts the hFE values will be tighter. Next batch you might measure something else. It's a moving target from a spice point of view. At best you could come up with three models for the same part: low gain, typical gain, high gain. You might do your basic checks against typical but then you need to make sure the circuit at least works with high and low gain cases.
The fine details of electronics is a headache. You can go a long way with ignorance is bliss philosophy but one day it will catch up with you. There's plenty of debugging threads on this forum with some very obscure problems, often they are very difficult to debug via forum posts.
> The current was inverted
Same thing either way. SPICE tends to use the notion of current "IN" to a part leg, so if you probe the other leg (of a 2-leg part) you get the complement. But usually the direction is "obvious by inspection". Water runs downhill; if we start with a dry ocean and water on the mountain then water runs to the sea and air flows up the mountain to replace it. Same with electrons and positive conventional current.
I rigged the plot with LOG to cover a huge range. Your LIN plot exposes a model oddity: it is three straight (resistive) segments, no blending. Easy to compute but physically unlikely.
Guys Just an update: I measured the VGSoff of the JFET's I got, and here are the values (I used 3.9 Megaohm resistor):
1: 1.245 V
2: 1.241 V
3: 1.270 V
4: 1.271 V
The factor of multiplication is somewhere around 1.85 from what I measured with the R.G Keen test. I guess I couldn't do it without you guys.
Another thing is, the biggest difference in VGSoff stays at 2.4%. Is it reasonable? Or for paying 8.5 Euro for a matched set I would expect better?
Thanks, Fred
QuoteAnother thing is, the biggest difference in VGSoff stays at 2.4%. Is it reasonable? Or for paying 8.5 Euro for a matched set I would expect better?
Anything better than 50mV is quite good.
Yours are 30mV worst case, so that's pretty good.
Quote
The general idea is covered here...
... just as you don't need to add .lib or .inc for the "builti-in" LTspice parts"
I followed the website and was able to add a model, thanks!
Nice explanation of your parts, I've already wrote down what you said here, if I will use it in the future.
Quote
They are only wrong if you interpret them as VGS_off... using the correction factor I calculated (or one like it).
Yeah, I understand now! Those values (R.G.) seemed right, because I saw that they were close to each other (but at the same time thought it was strange to get -0.7V VGSoff). But now I understand (thanks to you) that it's wrongly said VGSoff. So I would say that the real and best test would be the one you showed me, cause there's no reason to use the other.
Quote
OK I get it... I just do it less often.
Yeah, I actually got happy to be able to interpret the results and see that "no matter the input" the gain won't change. The why's for the +5dB stays for other time.
I imagine frustration and problems will never disappear, as you might be the proof of that (as you're telling me, not that I'd have anything close to your experience).
Quote
So the main problem is if you *never* check against reality you are just seeing numbers on the computer... When you plop down a whole heap of ICs with unverified models the results are hit and miss."
Pretty interesting... It makes all sense. With the LFO I actually am testing it alone (separated from the circuit) because spice doesn't do real time analyser as I'm aware (so I couldn't see the notches moving), but now I have even other reasons. Oh and when I want to use the "LFO voltage" in my circuit I change the bias voltage, in that way it's like the LFO was moving (or some place in the up's/downs of the wave).
I did Zener=4.8V source because what I wanted to test wasn't the power stage of the circuit but the LFO/Phasing part.
Also, I was thinking bout doing 555 in my circuit (as the comparator with the square output), but I don't know quite well how to use it... Either way, a very good idea would be to use a square wave generator as you mentioned it. Surprisingly, I was thinking bout asking here: Do you think it's a good idea to substitute the "obsolete" P90 triangular wave LFO for a 555 timer with na integrator? Or is there any significant drawback? My reasons would be because I searched and talked to some people who highly instructed me to use the 555.
Quote
There's a few sites on the web about converting datasheets to spice models
Pretty interesting... Wrote down.
Quote
Slope is about how well the Zener regulate, which is kind of it's job... but at least one which will match the circuit you build.
I imagine that... It's few information, which they are allowed to only give to be able to sell, if not, there's plenty of others saying that "they do better".
QuoteA lot of parts are not precisely defined... but then you need to make sure the circuit at least works with high and low gain cases."
This.. seems to be very important. As long as we know what to change in the model (to make it the worst or best scenarios), we should really do that testing of best/worst case.
Quote
You can go a long way with ignorance is bliss philosophy but one day it will catch up with you.
Won't forget this... Won't forget...
Quote
Same thing either way... Easy to compute but physically unlikely.
Yeah, seing it in LOG "looked like" the datasheets, meanwhile the LIN really shows some crappy moddeling (I would guess). But I don't know already, if that works for the current I wanted, that's alright, if not, i'll find a voltage source and done...
Quote from: Rob Strand on September 14, 2020, 09:24:11 AM
Anything better than 50mV is quite good.
Yours are 30mV worst case, so that's pretty good.
Nice!!!!! I'm expecting now another set of JFET's (because they just didn't arrive) and then I'm gonna probably choose the closest matches/bigger VGSoff possible.
QuoteAlso, I was thinking bout doing 555 in my circuit
Opamps are probably better as you can slow-down the switching transitions and they don't have strong current pulses on the supply rails. NE555's + audio need extra care.
Quote
Nice!!!!! I'm expecting now another set of JFET's (because they just didn't arrive) and then I'm gonna probably choose the closest matches/bigger VGSoff possible.
If you can get below 50mV it will sound right for sure.
JC Maillet (user E7b9) had some stuff on his web-site which lets you use mismatched JFETs. You add a bias pot to each JFET. It's more mucking about to adjust but it lets you use any old JFETs. You can even use a simplified version where you split the JFETs into two sorted groups: low Vgs_off and high Vgs_off. Then only have two trimpots to adjust (assuming the parts in each group are relatively close).
Quote
Opamps are probably better as you can slow-down the switching transitions and they don't have strong current pulses on the supply rails. NE555's + audio need extra care.
Hmm. interesting. What does the strong current pulses could cause? Easily fried resistors i guess? Cause I talked to a guy who works in building effect modules and stuff, and he explained me that the op-amp as I was using (in the triangular wave LFO) was not giving me exact square form wave, neither exact triangular form, and never would. Besides that, he said that the circuit has too much feedback, and the input of the op-amps, being BJT's, would oscilate too much and become unstable.. Does this make any sense?
If so, how bout the lm339? For audio it should make sense, right?
Quote
If you can get below 50mV it will sound right for sure... Then only have two trimpots to adjust (assuming the parts in each group are relatively close).
Could you write me the website? Or if you want, by message, I don't know.
Anyway, it could be a veery good idea to have pots to each JFET. As I already have a matched set, I don't think I will need to do it, yet.
...
Given all that, I already saw so much about the LFO's and studied about schmitt trigger, but I'm thinking it's a bit too complex for me to understand the schematics of the LFO on the Phase 90. It's like I get the idea, but the function of each resistor and how the op-amp part operates is something I'm not getting right.
One of the reasons for me wanting to change to a comparator is that. I don't seem to be confident enough to explain the operaton of the TL072 there it in a final presentation of college, as I don't exactly know what it does. Follows down the LFO schematic I'm refering to:
(https://i.postimg.cc/LYNV8Hnr/LFO.png) (https://postimg.cc/LYNV8Hnr)
QuoteWhat does the strong current pulses could cause?
You get clicks in the audio at the LFO rate. Some opamp designs do that.
QuoteIf so, how bout the lm339? For audio it should make sense, right?
You can only try it. You should be able to get it to work. Comparators usually have faster edges than opamps so there is more chance for the sharp transistions to get into the audio. The slow opamps tend to be slow by nature.
Quote
Could you write me the website? Or if you want, by message, I don't know.
Anyway, it could be a veery good idea to have pots to each JFET. As I already have a matched set, I don't think I will need to do it, yet.
It's here. This method offers the best results for mismatched JFETs. However if your JFETs are reasonably matched you don't need to go so far.
https://viva-analog.com/viva-analog-paradigm-shifter-jcmc-2017/
Quote
Given all that, I already saw so much about the LFO's and studied about schmitt trigger, but I'm thinking it's a bit too complex for me to understand the schematics of the LFO on the Phase 90. It's like I get the idea, but the function of each resistor and how the op-amp part operates is something I'm not getting right.
One of the reasons for me wanting to change to a comparator is that. I don't seem to be confident enough to explain the operaton of the TL072 there it in a final presentation of college, as I don't exactly know what it does. Follows down the LFO schematic I'm refering to:
Go here, go to the bottom of the page,
https://www.electrosmash.com/mxr-phase90
R19 and R21 set the upper an lower threshold of Schmitt trigger. One threshold when the opamp output is high an one when it is low. You use the voltage divider equation with R19 and R21 to get the voltage on U1b's + input. When the cap voltage reaches one of those thresholds the output of the opamp changes state. That causes the cap to charge or discharge in the opposite direction until it hits the other threshold.
For understanding, ignore C7 and R24, their purpose is to slow down the transistions which helps avoid clicks. They to affect the behaviour a little bit.
The trimpot set the DC level to the JFETs.
The 3M9 resistor and the 1M resistor (+added trimpot) mix the DC from the trimpot and the LFO output.
From the perspective of the JFET gates, the 1M(+added trimpot) doesn't affect the DC level so much. However for the LFO, the 1M(+added trimpot) form a divider so when the trimpot is set to a low value it reduces the amount of LFO signal getting to the gates. Similarly when the trimpot is set to a high value the divide lets more LFO signal through to the gates.
A small detail is the LFO waveform is a "triangular" waveform plus a DC offset of about 4.5V. That comes about because the circuit is single supply. The DC offset does have an effect on the JFET biasing. The bias trimpot has enough adjustment to factor in that fixed DC component.
Quote from: Rob Strand on September 15, 2020, 07:41:03 PM
The get clicks in the audio at the LFO rate. Some opamp designs do that.
Wow this would be really bad..
QuoteYou can only try it... The slow opamps tend to be slow by nature.
Yeah, I would have to try it in physical reality. So between TL072, LM393/339 and NE555 you would reccomend better the TL072 right?
QuoteIt here...
https://viva-analog.com/viva-analog-paradigm-shifter-jcmc-2017/
Thank you. Already took a look at it seems a endless fountain of information for me.
Quote
R19 and R21 set the upper an lower threshold of Schmitt trigger. One threshold when the opamp output is high an one when it is low. You use the voltage divider equation with R19 and R21 to get the voltage on U1b's + input.
Ok, fair enough! What do you mean by voltage divider equation with R19 and R21? How do you come to that equation?
Quote
When the cap voltage reaches one of those thresholds the output of the opamp changes state. That causes the cap to charge or discharge in the opposite direction until it hits the other threshold.
Alright, that I can deal with. But we're talking about the C10, right?
And, I know you said to ignore C7 and R24, but how do they prevent those clicks? I can't see how..
Quote
From the perspective of the JFET gates, the 1M(+added trimpot) doesn't affect the DC level so much.
What do you actually mean? Because the 1M+trim will give the DC "level" necessary to make the FET's vary, in other words, will deliver voltage to the gate of the FET's, right? So how can it not affect level?
Quote
However for the LFO, the 1M(+added trimpot) form a divider so when the trimpot is set to a low value it reduces the amount of LFO signal getting to the gates. Similarly when the trimpot is set to a high value the divide lets more LFO signal through to the gates.
I don't quite understand it.. It seems to me that what one would want would be that the LFO came to the gates of the FET's and that, with it's span of voltages, that it would make the FET vary, isn't that? Because if I get more/less LFO signal (meaning level) on the gates, what does it mean, implies?
Quote
A small detail is the LFO waveform is a "triangular" waveform plus a DC offset of about 4.5V. That comes about because the circuit is single supply. The DC offset does have an effect on the JFET biasing. The bias trimpot has enough adjustment to factor in that fixed DC component.
It's a little confuse to me, the offset it's caused by what? It's the output of the op-amp? And how does the trimpot would adjust the factor? Is there any position where it would adjust less/not adjust?
All of these questions i'm bringing took in consideration that I already did some simulation on the P90 LFO but didn't manage to understand some parts/some responses of the circuit.
QuoteYeah, I would have to try it in physical reality. So between TL072, LM393/339 and NE555 you would reccomend better the TL072 right?
The TL072 is fine there's plenty of opamp choices, pretty much any opamp will work.
QuoteWhat do you mean by voltage divider equation with R19 and R21? How do you come to that equation?
There's many ways to look at it, however looking it as a resistive mixer covers the Schmitt trigger and the combination of the bias Trimpot + LFO
https://www.allaboutcircuits.com/textbook/semiconductors/chpt-8/averager-summer-circuits/
Consider the case where you only have two voltage sources V1 and V2 and they feed their corresponding resistors R1 and R2. The voltage at the output is a blend of the two input voltages.
Vout = (R2/(R1+R2)) V1 + (R1/(R1+R2)) V2
If you look at only one of the voltages, say V1, with no V2, you get a simple voltage divider equation,
Vout = (R2/(R1+R2)) V1
If you view circuit from V2's perspective, with no V1, you also get a voltage divider equation,
Vout = (R1/(R1+R2)) V2
The two input circuit is just the sum of both those separate results. That works because of superposition theory.
You can also view this as a blender,
Vout = k * V1 + (1-k) V2; where k = R2/(R1 + R2)
k always between 0 and 1 depending on the resistor values.
k=1 select V1, k=0 select V2, k=1/2 is equal amounts of V1 and V2
For the schmitt trigger case,
V1 = the opamp output voltage, which is either 0V or 9V ; actually more like 1V or 8V
V2 = Vref = 4.7V
R1 is R21 in the schematic
R2 is R19 in the schematic
From the two opamp voltage you calculate two voltages on U1b's +input and they are the thresholds.
QuoteAlright, that I can deal with. But we're talking about the C10, right?
Yes.
QuoteAnd, I know you said to ignore C7 and R24, but how do they prevent those clicks? I can't see how..
It'a hard to expain. When the opamp output tries to change state the cap C7 shifting the voltage. Kind of like pulling a piece of cheese on a string that a mouse is trying to get. Have a play in spice with different C7 values.
QuoteWhat do you actually mean? Because the 1M+trim
..
It's a little confuse to me, the offset it's
If you look at this circuit as a resistive mixer, similar to the above,
Output = JFET gate voltage
V1 = Bias Trimpot
R1 = 1M + adjustment trimpot
V2 = LFO out
R2 = 3M9 resistor.
The LFO output can be broken down in to and AC component and a DC component,
VLFO = VLFO_AC + VLFO_DC
The gate voltage is then,
VGS = k * VBIAS + (1-k)*VLFO
= k * VBIAS + (1-k)*( VLFO_AC + VLFO_DC)
= {k* VBIAS + (1-k)*VLFO_DC} + { (1-k) VLFO_AC}
From the perspective of the JFET gate,
- the first {} is the true DC level and it depends on the bias trimpot adjustment and the also the DC level coming out of the LFO.
- the second part shows how much AC part of the LFO get through. ie. the how the peak to peak at the LFO output
gets reduced by a factor (1-k) before getting to the JFET gate.
Since the 3M9 resistor is somewhat larger the the 1M you will find k is about 0.8, so 1-k is 0.2
so the LFO swing at the gate is reduced somewhat compared to the swing the LFO output.
Quote from: Rob Strand on September 16, 2020, 07:37:33 PM
.
Just something quick, is there anyway I can contact JC Maillet, the owner of the site you wrote me, personally? Because I looked at the explanation of his circuit of unmatched JFET's and I was completely buzzed about it. In a sense that it's very well done and he seems to know a looot about phasers, which could help me in this stage.
(I know he's a user here but I don't know how to reach personally).
So I have good news.
(The numbers of components R21, R19 etc come from the electrosmash schematic)
Before I start showing what I got in sims, let me say I did the math you instructed me to, and taking note that the op-amp would give me 0.1V to 8.9V in the output in the best case (and a 4.8 Zener), I got 3.663 V and 5.792 V as the thresholds in the Vout of the summer/blender, as the following image indicates (but not exact values of course, with a difference of 0.3V):
(https://i.postimg.cc/21R7rGxN/Vout-summer.png) (https://postimg.cc/21R7rGxN)
Now I can understand what you told me about the blender.
Following, I wanted to sim for my own FET's which are matched, and knowing that they are around -1,23 VGS-off, I knew I would want almost 1.23 Voltage span for my LFO (which I wasn't getting at all).
In that matter, I could calculate the Gate Voltages I would want: the less (in module) is 0V and the most is around -1.23 V.
For that to happen I need 4.8V and 3.57V coming from the LFO, respectively (taking account of 4.8V Zener).
For me to get to the part I want (outputing desired LFO voltage on the gates) I needed to tweak around the thresholds of the Schmitt Trigger and at the same time tweak with the Bias Voltage, so I did some simulation as will follow after the resume below:
R19 R21 LFO voltage span Shape of the triangular wave
1- 150k 470k 0.33 Vpp very good
2- 470k 470k 0.62 Vpp good
3- 470k 150k Almost 1Vpp not so good
4- 150k 800k 0.25 Vpp very good
5- 800k 150k 1Vpp aproximmately not good
sims (respective to the numbers above):
(https://i.postimg.cc/WFw3Pjjx/LFO-R19-R21-1.png) (https://postimg.cc/WFw3Pjjx)
(https://i.postimg.cc/z3qvFLFN/LFO-R19-R21-2.png) (https://postimg.cc/z3qvFLFN)
(https://i.postimg.cc/3W9RSKtv/LFO-R19-R21-3.png) (https://postimg.cc/3W9RSKtv)
(https://i.postimg.cc/nCPLx3bV/LFO-R19-R21-4.png) (https://postimg.cc/nCPLx3bV)
(https://i.postimg.cc/dhZVVGw2/LFO-R19-R21-5.png) (https://postimg.cc/dhZVVGw2)
My conclusion is that I don't really need a perfect triangular wave so I've chosen 470k and 470k to start tweaking with. As I had better voltage span but not still the values I wanted I started tweaking with Bias and R20.
It wasn't very linear but with:
R19 R21 R20 VBias
470k 470k 2mega 4.0V
Which is this schematic:
(https://i.postimg.cc/nM1k3D8G/LFO-R19-R21-R20-Vbias-1.png) (https://postimg.cc/nM1k3D8G)
I got what I wanted:
(https://i.postimg.cc/Fd4yZ9D6/LFO-R19-R21-R20-Vbias-sim.png) (https://postimg.cc/Fd4yZ9D6)
I'm only guessing the LFO on the P90 was just like that in the schematic because there were some poor jFET's with like -0.4 VGS-off that made it to the fabric. Other than that, if one doesn't change things to his/her behalf, it will get hard to get the full behaviour of the jFET's ohmic region.
Quote from: savethewhales on September 17, 2020, 08:29:02 AM
Just something quick...
a few key points
(... )
for decades now there's been this misleading (I'd say almost completely false) methodology perpetrated by guys with no real knowledge of circuit analysis and theory ... I've read many of the early sources and it's the same basic narrative over and over // often seemingly repeating manufacture application/marketinng notes that were written in a way intended not to reveal too much ... get my drift ?
phasor circuit design/behavior is a lot simpler than it's often made to appear, especially when the right design methodology is in place ... the key is to start out by separating the phasor system into its three constituent parts
---
If you *really* want to understand what's going on inside a phasor I would strongly recommend staying in the time domain at first - that's where the usual first mistake lies ... If you *really truly* want to understand what's going on inside a phasor get yourself a signal generator and dual-input scope and breadboard up a simple two-stager controlled from a dual 250k pot and "see for yourself" what happens to a sine wave against manual resistance variation ... then we'll have something beyond magical hand-waving to talk about // everything necessary for making the right conclusions will be there in front of you
next,
time to get past the resident fiasco that is jFET testing
recognize that I have strong views surrounding the unexplained magic that passes for a bone-fide test in this forum ... once you can get passed that idea read the Vishay paper on VCR use of jFET's and consider why the test that I and many other people recommend doing results in extracting two key (fixed) numbers for each device ...
here's a popular technique for estimating Vgs(off) that uses the high internal resistance of a DMM's volt meter to bias the jFET at ultra low-current levels:
https://viva-analog.com/jfet-characterization-technique-using-only-9v-battery-and-dmm/ (https://viva-analog.com/jfet-characterization-technique-using-only-9v-battery-and-dmm/)
simply put, any test that returns a single number must be wrong by virtue of the fact that jFET's have a two-dimensional error space // ... a conclusion that's beyond opinion or preference
furthermore, this two-part knowledge applies similarly to jFET's living inside active voltage gain stages (in particular, applying to recent questions about jFET linearity, input headroom, mu-stage transfer, etc ... all answered starting from this basic analysis) ...
there is no intelligent way around any of this
>>> for reference, these are same numbers (variables) that are listed in the Vishay paper, the same that are listed in textbook jFET equations, the same that are listed in data sheets ... strangely, this forum is the only place I know of where jFET's are not regarded in terms of their measured/estimated Vgs(off) and Idss values ... perhaps the reason for the recurring struggle we see here, in particular with jFET phasors
once you understand the Vischay "VCR" paper you'll understand that all jFET's are being controlled (or intended to) by a voltage that takes Vgs "somewhere" inside the Vgs(off)-to-0 range ... Vgs(off) being negative for n-channel devices ... how much of that somewhere being covered depends on the design ... for example, my MXR Phase90 LFO sim served to give specifics not seen elsewhere about that very key aspect ...
the Vishay paper makes it clear that we can talk in terms of a (normalized) control range percentage, all I'm doing in my Paradigm Shifter is using trim-pots to scale the control range on the device with the largest Vgs(off) value down to match subsequent Vgs(off) values that are not the same (and smaller) ... in the process matching the range percentage and relative idling location within each Vgs(off)-to-0 span ... in normalized terms, the same ...
no brainer \
*and fairly accurate as long as you use a meter with a high Zin like Rob pointed out last time
as for the control part of phasors I would encourage you to experiment and come up with your own way of interfacings things, as long as you understand the need to keep your gates in that Vgs ball-park now that you understand how all that works ... understand that when you do proper (high accuracy) jFET testing you end up with lot less false positives in the end ... which means going thru a truckload of devices just to get a good matched quad - hence the pull towards proportional scaling of the Vc control line
hope this helps
---
btw, here's a recent offshoot from my 2n5457 characterization work ...
providing an obvious solution to a basic re-design problem
https://viva-analog.com/viva-analog-1176x-jcmc2020/ (https://viva-analog.com/viva-analog-1176x-jcmc2020/)
Walter Becker's turf ...
Quote from: Eb7+9 on September 17, 2020, 07:28:31 PM
a few key points
(... )
Wow thanks for answering.. I really apreciatte that. I don't even know how to start.
QuoteIf you *really truly* want to understand what's going on inside a phasor get yourself a signal generator and dual-input scope and breadboard up a simple two-stager controlled from a dual 250k pot and "see for yourself" what happens to a sine wave against manual resistance variation ...
I really really do, but actually don't have a scope here in my home, so I must be left with simulations on LTSpice...
Quote
next,
time to get past the resident fiasco that is jFET testing
hope this helps
I actually read the whole paper and read all that you wrote. And it's really reasonable to measure the jFET's in two variables, so I've actually measured it in the way you recommended it (see in computer for better visualization of table):
Number of jFET VGS-off Idss(the negatives should be from polarity)
1 1.304 V -2.29 mA
2 1.283 V -2.36 mA
3 1.306 V -2.22 mA
4 1.276 V -2.33 mA
It's actually funny that this is my 3rd type of measurement of JFET's, and of course, the measurements are different from the last one, which are diff from the first, you know it..
Another thing is the seller wrote in a plastic: "2N5457 2.5 mA 1.2 V".. I have nothing to say about it.
It seems that the VGS-off values and Idss values are kinda close, which for me is actually sacred.
After reading the Vischay paper, I got to know a better way of not having distortion and having a more linear Rds curve, it's just that I don't look for anything too precise, in the sense that I am okay with having not so much headroom and maybe not so linear variation of Rds because I am just doing a project to college, I don't know how I would put those extra sources on the gates, and it's my first project of building electronics.. On top of that, I don't have very much time left.
That being said, all I want is t know what limits do I have to set my pedal for it to work fine and in the full range of the jFET's. I guess with the measurements above I could be fine.
The biggest reason why I wanted to reach you is because of the LFO, in the sense that it's very very sketchy (the original), and the explanations I see on the internet (apart from Rob's explanation) are incomplete and hard to explain in a presentation. I have simulations on the LFO done on a post of mine above, and will post more (regarding behaviour of C7 and R24).
Do you think the LFO circuit of the Phase 90 (with some tweaks, as I did) would be enough for me to oscillate from -0.2 VGS to -1.3/-1.4 VGS? Or it seems too hard to obtain given the limitatons of the LFO circuit?
Or do you have any other advice to give me regarding LFO, that could be better for me?
I already talked to lot of people, including my teacher and the options were letting it as it is, using NE555 or LM393. As I don't want tooo much precision (just something looked/felt like a triangle), I thought about staying with the TL072 and integrator.
Anyway after all this I would kindly ask you how can I reach you beyond this web site, maybe e-mail or whatever you would like, because I read your web-site post of Paradigm Shift and other things of yours (LFO sim and 2N5457 testing) and looks like you are experienced in the area/in phasors, and that's what I need the most to get things right now.
Thank you very much.
Quote from: Rob Strand on September 16, 2020, 07:37:33 PM
It'a hard to expain. When the opamp output tries to change state the cap C7 shifting the voltage. Kind of like pulling a piece of cheese on a string that a mouse is trying to get. Have a play in spice with different C7 values.
As usual, here are my simulations (only changing C7 and keeping things as they were for triangle between 3.6 and 4.8V).
Number of sim/image C7 Value Comment
1 0.01uF no delay
2 0.1uF >1.2 seg delay
3 0.5uF Even with 40 seg sim no change
4 1nF Small delay (now smaller capacitor)
5 0.1nF >1.5 seg Delay (smaller cap)
(https://i.postimg.cc/ykrrK8QD/LFO-C7-1.png) (https://postimg.cc/ykrrK8QD)
(https://i.postimg.cc/gxCSwBPd/LFO-C7-2.png) (https://postimg.cc/gxCSwBPd)
(https://i.postimg.cc/JyjTjc1X/LFO-C7-3.png) (https://postimg.cc/JyjTjc1X)
(https://i.postimg.cc/cgZFhgHb/LFO-C7-4.png) (https://postimg.cc/cgZFhgHb)
(https://i.postimg.cc/DJgBMv4y/LFO-C7-5.png) (https://postimg.cc/DJgBMv4y)
(Don't know how to put the images bigger).
As I can conclude, I couldn't seem to find anything reasonable to explain the bigger delays when the values of the cap differ too much from the original 0.01 uF positive or negatively..
But for experimentation, I could see that I would want to use the 0.01 uF cap, no more explanation possible. If someone knows the reasons behind these results please let me know. Thanks.
Quote from: Rob Strand on September 16, 2020, 07:37:33 PM
If you look at this circuit as a resistive mixer, similar to the above... so the LFO swing at the gate is reduced somewhat compared to the swing the LFO output.
Perfect explanation. But there's always something more for me to search. In this case, where do you get the DC level coming out of the LFO? What sets it?
I ask this because I wanted to do the math, but without that I can't.
Although, without the LFO DC I could already calculate the percentage of AC passing through the gates, given the resistor network that I have on my schematic:
(https://i.postimg.cc/756KhGt3/resistor-network.png) (https://postimg.cc/756KhGt3)
However I did math, with k=0.3 following your logic, and 1-k=0.7. With those values, I get
AC of 4.27Vmax to 2.233Vmin, from which I calculated the diifference to know Vpp and it's 2.037, differently from my simulations which give me 4.62Vmax and 3.43Vmin, with a peak to peak voltage of 1.19 V.
Could I be doing something wrong?
Thanks, Fred
QuoteAs I can conclude, I couldn't seem to find anything reasonable to explain the bigger delays when the values of the cap differ too much from the original 0.01 uF positive or negatively..
But for experimentation, I could see that I would want to use the 0.01 uF cap, no more explanation possible. If someone knows the reasons behind these results please let me know. Thanks.
I recommend looking up how to set the initial conditions in spice. You need to set IC=5V or IC=0.1V on C2. The add UIC to the .TRAN analysis.
Start-up for oscillators in Spice is tricky. They can do things that the real circuit doen't do. Imagine inside the opamp there is transistors and JFETs. In reality all those parts are slightly different. However in Spice they are exact. When the circuit powers up in spice it is "too symmetrical" there's is nothing to bias it to make it go one way or another. It's like balancing a pin on he sharp point. If the math is exact you can do it but in practice you cannot. Also the electrical noise in each part of the the circuits different. In spice you have rounding errors which can make the circuit behaviour changes and eventually start.
QuoteIn this case, where do you get the DC level coming out of the LFO? What sets it?
The connection of R19 to Vref is the main that *sets* the DC level. Apart from that, the opamp saturation voltages can affect the DC point but you have no control over these. *if* you wanted to shift the DC point you can connect R19 to a different voltage. Another way is to add a resistor from the opamp + input to +V or ground.
If you move the DC level away from Vcc/2 the timing capacitor will charge asymmetrically and that will mean the time to ramp-up with start to differ from the time to ramp down. The square output will not be square.
A bigger problem is the DC output from the LFO depends on the battery state. If the DC bias depends on the battery the bias adjustment becomes mis-adjusted when the battery goes flat. The DC from the bias trimpot does not change with the battery state as much because the Zener helps regulate the voltage. The MXR design makes R19 small so the LFO DC level is closer to Vref and less dependent on the battery.
QuoteHowever I did math, with k=0.3 following your logic, and 1-k=0.7. With those values, I get AC of 4.27Vmax to 2.233Vmin, from which I calculated the diifference to know Vpp and it's 2.037, differently from my simulations which give me 4.62Vmax and 3.43Vmin, with a peak to peak voltage of 1.19 V.
Could I be doing something wrong?
For 470k + 470k I get k = 0.5 and 1-k = 0.5. VLFO = 6.3V and 2.85V
For 150k + 470k I get k = 0.24 and 1-k=0.76. VLFO = 5.5V and 3.8V
Quote
I recommend looking up how to set the initial conditions in spice. You need to set IC=5V or IC=0.1V on C2. The add UIC to the .TRAN analysis.
...
In spice you have rounding errors which can make the circuit behaviour changes and eventually start.
Tommorow as soon as I can I will do the simulations.
But, you're telling me these "delays" are non-reality? So what does the C7 affect then?
Quote
The connection of R19 to Vref is the main that *sets* the DC level... The MXR design makes R19 small so the LFO DC level is closer to Vref and less dependent on the battery.
So how do I know that R19 is bringing DC to the circuit? Because of the current that comes from the 1Mresistor+Trimpot that enters the LFO? Because I'm not seeing any other way around...
One important thing is the zener then, for setting the DC more stable... Ok.
I actually will use a switcher between 9V source and a battery, so there shouldn't be a big problem.
Quote
For 470k + 470k I get k = 0.5 and 1-k = 0.5. VLFO = 6.3V and 2.85V
For 150k + 470k I get k = 0.24 and 1-k=0.76. VLFO = 5.5V and 3.8V
Rob, I was actually doing the math for the input of the Gate Voltages (which are different from the output of the LFO) with these maths that you quoted. The maths that you did I also did somewhat above that, with similar, if not the same results.
But thanks anyway!
QuoteBut, you're telling me these "delays" are non-reality? So what does the C7 affect then?
The delays you are see are not realistic, they occur because the mathematical exactness of spice make it difficult for the oscillator to start. There are delays associated with C7. They occur on a small time scale 150k * 10nF = 150uS. That enough to slow down the edges of the opamp. If you put in 1uF the delays are 150k * 1uF = 150mS. That will start to change the frequency of the LFO a bit.
QuoteSo how do I know that R19 is bringing DC to the circuit? Because of the current that comes from the 1Mresistor+Trimpot that enters the LFO? Because I'm not seeing any other way around...
Current doesn't come from R19. R19 *determines* the voltages on the timing cap. Current can come from the opamp output via R2 on your schematic (R36 on electrosmash link).
As an experiment try connecting a resistor (say the same size as R2 on your schematic) from the timing cap to ground and then to Vcc. Notice how the cap voltage swings to the same peak voltages but on and off timing ratios are changed.
The DC offset from the LFO can be a little confusing because it depends on how you look at it:
If the average level at the output of the oscillator is Vref, you can consider the DC level Vref. Since the JFET
drain source is at VREF the LFO DC level has little effect. In the real circuit it has a small effect because the oscillator DC level isn't quite at Vref.
The other way to look at the LFO is to think of the minimum voltage as a DC offset. The reason you would think like this is because the most critical part of the circuit is the JFET voltage when is gets close to Vgs_off. This is when the JFET resistance is the highest. That occurs when the LFO is the lowest output. If the minimum voltage changes because you have played with the part values then you would need to adjust the bias trim pot to compensate.
It might be a little confusing. The whole reason you need matched JFETs is so the JFET resistance tracks when the JFET voltage is at the lowest point. In this region small changes in the gate voltage produce large changes in the JFET resistance.
Quote from: savethewhales on September 18, 2020, 06:24:15 PM
Tommorow as soon as I can I will do the simulations.
So I did it. Thanks to you Rob, for advising about the initial conditions.
The sims were with this circuit:
(https://i.postimg.cc/H8W7XwTW/19-9-teste-C7-circ.png) (https://postimg.cc/H8W7XwTW)
First, messing with C7.
C7 Comment
1- 0.01uF very good
2- 0.1 uF Less sharp
3- 0.5 uF Way less Sharp
4- 1 nF very good
5- 0.1 nF very good
6- 0.01 nF very good
(in order):
(https://i.postimg.cc/dkNJNr8V/19-9-teste-C7-1.png) (https://postimg.cc/dkNJNr8V)
(https://i.postimg.cc/R3M9MXd0/19-9-teste-C7-2.png) (https://postimg.cc/R3M9MXd0)
(https://i.postimg.cc/bZ0pcKQM/19-9-teste-C7-3.png) (https://postimg.cc/bZ0pcKQM)
(https://i.postimg.cc/qNH4FkCy/19-9-teste-C7-4.png) (https://postimg.cc/qNH4FkCy)
(https://i.postimg.cc/Sj5yWLSZ/19-9-teste-C7-5.png) (https://postimg.cc/Sj5yWLSZ)
(https://i.postimg.cc/xNknw8Ry/19-9-teste-C7-6.png) (https://postimg.cc/xNknw8Ry)
Now sim messing with R24.
R24 Comment
1- 150k very good
2- 50k very good
3- 10k very good
4- 700k Less Sharp
5- 1.2 mega Less Sharp
6- 3.3 mega Less Sharp
7- 10 mega way less sharp
(in order):
(https://i.postimg.cc/R3FS7gHD/19-9-teste-R24-1.png) (https://postimg.cc/R3FS7gHD)
(https://i.postimg.cc/MMnGS9ZQ/19-9-teste-R24-2.png) (https://postimg.cc/MMnGS9ZQ)
(https://i.postimg.cc/CZPKX300/19-9-teste-R24-3.png) (https://postimg.cc/CZPKX300)
(https://i.postimg.cc/zykvSLPV/19-9-teste-R24-4.png) (https://postimg.cc/zykvSLPV)
(https://i.postimg.cc/PPjd3XDZ/19-9-teste-R24-5.png) (https://postimg.cc/PPjd3XDZ)
(https://i.postimg.cc/XZzVQ9K7/19-9-teste-R24-6.png) (https://postimg.cc/XZzVQ9K7)
(https://i.postimg.cc/hX8zyZh4/19-9-teste-R24-7.png) (https://postimg.cc/hX8zyZh4)
I guess I can conclude that the resistor with the capacitor form a filter for the output of the schmitt trigger in a sense that they reflect the sharpness of the transitions on the op-amp. Am I right? And is it a simple RC filter, or smth else?
Thanks
Quote
The delays you are see are not realistic... That will start to change the frequency of the LFO a bit.
Ok. Yeah actually that was exactly what I simulated in the post above. greater values of Cap, worse edge of the wave.
Quote
Current doesn't come from R19. R19 *determines* the voltages on the timing cap. Current can come from the opamp output via R2 on your schematic (R36 on electrosmash link).
As an experiment try connecting a resistor (say the same size as R2 on your schematic) from the timing cap to ground and then to Vcc. Notice how the cap voltage swings to the same peak voltages but on and off timing ratios are changed.
First sim gave me two equal results:
(https://i.postimg.cc/qhqX5QwY/teste-r36-ground.png) (https://postimg.cc/qhqX5QwY)
(https://i.postimg.cc/34qC5pbw/teste-r36-Vcc.png) (https://postimg.cc/34qC5pbw)
Gonna try to mess with the initial times (take them off):
(https://i.postimg.cc/GB9DjtqJ/teste-r36-ground-icoff.png) (https://postimg.cc/GB9DjtqJ)
(https://i.postimg.cc/wtPm4zrK/teste-r36-Vcc-icoff.png) (https://postimg.cc/wtPm4zrK)
I'm getting same responses.. I guess I'm doing it wrong then. Circuit:
(https://i.postimg.cc/ThjKgnTv/aaaaaaaaaaaa.png) (https://postimg.cc/ThjKgnTv)
Quote
The DC offset from the LFO can be a little confusing because it depends on how you look at it... In this region small changes in the gate voltage produce large changes in the JFET resistance.
When you said drain, you meant source, right?
Well, actually with the way that I'm biasing the whole thing, the average value of the LFO output is at 4.65 V, almost Vref which stays at around 4.8.
As for the jFET resistance, that part i'll be honest and say that I understood already, I even designed the circuit (to simulate) in a way that the lowest voltage that goes to the gate, can pass downwards the lowest possible (3.5 Volt in my case because I have my FET's at a VGS-off of 1.3 V), as the 22k in parallel makes it not change too much above it. However, I designed it to not pass 4.6 Volt upwards of gate input, meaning that It doesn't pass -0.2 VGS upwards, because I would have way too low resistance value, meaning a cutoff frequency of above 20k Hz (which i'm not interested at all).
I calculated the resistance as being 432 ohms, but there's no way to calibrate the circuit other than at eye, when I'm beside an oscilloscope.
QuoteFirst sim gave me two equal results:
Gonna try to mess with the initial times (take them off):
I'm getting same responses.. I guess I'm doing it wrong then. Circuit:
The added resistor doesn't connect in series with cap. The added resistor connects to the upper side of the cap then to Vcc or gnd. The purpose of the exercise is to show that if you put current in or draw current out of the LFO output (ie. at the cap) it affects the LFO duty cycle but does not affect the output swing. It's not an improvement or mod. It shows what happens when you load down the LFO.
QuoteWhen you said drain, you meant source, right?
Yes, sorry about that.
Quote
Well, actually with the way that I'm biasing the whole thing, the average value of the LFO output is at 4.65 V, almost Vref which stays at around 4.8.
As for the jFET resistance, that part i'll be honest and say that I understood already, I even designed the circuit (to simulate) in a way that the lowest voltage that goes to the gate, can pass downwards the lowest possible (3.5 Volt in my case because I have my FET's at a VGS-off of 1.3 V), as the 22k in parallel makes it not change too much above it. However, I designed it to not pass 4.6 Volt upwards of gate input, meaning that It doesn't pass -0.2 VGS upwards, because I would have way too low resistance value, meaning a cutoff frequency of above 20k Hz (which i'm not interested at all).
I calculated the resistance as being 432 ohms, but there's no way to calibrate the circuit other than at eye, when I'm beside an oscilloscope.
In spice you can measure the minimum LFO voltage then replace the LFO with a fixed voltage of that value and look at the response. As for the real device, yes, it's tricky setting-up the circuit because the LFO is modulating all the time. Most people set it up by ear.
Quote from: PRR on September 08, 2020, 09:43:21 PM
Quote from: Rob Strand on September 08, 2020, 07:26:12 PM...the zener voltage is 4.8V and not the 5.1V on the label. ... problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!
Yes, don't trust SPICE at all, or its models.
The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.
Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.
(https://i.postimg.cc/xcr9QPQs/1-N750-plot-42.gif) (https://postimg.cc/xcr9QPQs)
Guys I'm sorry for bringing this here now after that much time, but where does the 0.4 mA come from? The 9V with the 10k resistor isn't supposed to give 0.9 mA?
Thanks
So, I've started to simulate the LFO together with the power supply in the circuit, and I've noticed that the real circuit gives at the gates of the FET's a wave that is way less triangular than supposed (even with tweaking the cap that sets the edges of the wave). The simulations (with explanation), come below.
This is what i'm getting:
Resistance Connection
1 - 1Meg Power Supply
2 - 2.7 Meg Power Supply
3 - 1Meg 4.8 Volt Source (simulating Zener Volt.)
4 - 2.7 Meg 4.8 Volt Source (simulating Zener Volt.)
(https://i.postimg.cc/CRsms6M0/Teste-aliment-VGate-1.png) (https://postimg.cc/CRsms6M0)
(https://i.postimg.cc/jwLcKxHq/Teste-aliment-VGate-2.png) (https://postimg.cc/jwLcKxHq)
(https://i.postimg.cc/2qHGPbBX/Teste-aliment-VGate-3.png) (https://postimg.cc/2qHGPbBX)
(https://i.postimg.cc/3yr9SCWv/Teste-aliment-VGate-4.png) (https://postimg.cc/3yr9SCWv)
Does anyone have any guess on why this is happening? Thanks.
> The 9V with the 10k resistor isn't supposed to give 0.9 mA?
9V at one end, 5V at the other end. 4V difference.
Quote from: PRR on September 21, 2020, 04:43:04 PM
> The 9V with the 10k resistor isn't supposed to give 0.9 mA?
9V at one end, 5V at the other end. 4V difference.
Ok, true!
Quote
The added resistor doesn't connect in series with cap. The added resistor connects to the upper side of the cap then to Vcc or gnd. The purpose of the exercise is to show that if you put current in or draw current out of the LFO output (ie. at the cap) it affects the LFO duty cycle but does not affect the output swing. It's not an improvement or mod. It shows what happens when you load down the LFO.
The sims go below:
Circuit:
(https://i.postimg.cc/TpSMzZ0q/Teste-R36-massa-circ.png) (https://postimg.cc/TpSMzZ0q)
R36-Vcc
(https://i.postimg.cc/TphvHRV3/Teste-R36-Aliment.png) (https://postimg.cc/TphvHRV3)
R36-Ground
(https://i.postimg.cc/yDZ4svrq/Teste-R36-massa.png) (https://postimg.cc/yDZ4svrq)
I'm afraid I coudn't take a conclusion out of these sims.
Quote
In spice you can measure the minimum LFO voltage then replace the LFO with a fixed voltage of that value and look at the response. As for the real device, yes, it's tricky setting-up the circuit because the LFO is modulating all the time. Most people set it up by ear.
Yeah! I was doing that before!
Now I'm actually using the normal circuit and putting a initial condition which reflects the voltage that I want to look at (hint: it works).
When i'm with an oscilloscope I guess it'll be easier for me to set up things.
With the sims I'm doing, I'm seeing that the Rds is changing drastically near the Vgs-off point, meaning that it reaches hundreds of ohms (500 below with my calculations) pretty darn fast, which if it was real (not just the simulation), it would leave me with a very poor voltage span (I was thinking 1.1 Voltage span for my -1.3 VGS-off jFETS, but I would have to have something like a 0.3 Voltage span because of the rate of change of rds).
Do you think this is normal in the physics of the component or is it something that can happen due to simulation/approximations/models?
Thanks Rob
Something curious:
With this circuit (almost equal to the Phase90 LFO):
(https://i.postimg.cc/N91c6yGL/Circuit-LFO-SIM.png) (https://postimg.cc/N91c6yGL)
I did a transient analysis, to see the voltages at every node since the potentiometer of Bias.
The result is this:
(https://i.postimg.cc/87JPFzvf/SIM-Voltages-LFO-Bias.png) (https://postimg.cc/87JPFzvf)
Which in my conclusion means that the voltage in the output of the trimmer is not fixed, and the LFO only works because of that change. In this case I guess I can conclude that theres more than one feedback loop in this circuit, which seems really hard to understand and calculate..
QuoteWith the sims I'm doing, I'm seeing that the Rds is changing drastically near the Vgs-off point, meaning that it reaches hundreds of ohms (500 below with my calculations) pretty darn fast, which if it was real (not just the simulation), it would leave me with a very poor voltage span (I was thinking 1.1 Voltage span for my -1.3 VGS-off jFETS, but I would have to have something like a 0.3 Voltage span because of the rate of change of rds).
Do you think this is normal in the physics of the component or is it something that can happen due to simulation/approximations/models?
Normally you see Rds *increasing* more rapidly as you approach Vgs_off. The drain resistance is,
rds = rds0 / (1 - |Vgs|/|Vp|) ; where rds0 = 1/Yfs0 and is typically around 200 ohms
The resistor (20k to 30k) in parallel with the JFET limits the rise.
For a typical vintage phaser the JFET rds is probably around 10k ohm to 12k ohms. So if you reverse that calculations that means |Vgs|/|Vp| is 0.98. 2% error of adjustment in Vbias will give |Vgs|/|Vp|=0.96 and that is going to drop rds to 5k ohms. So 2% adjustment error is causing 100% change. It's extremely sensitive.
It's unlikely you will be able to eye-ball the oscilloscope voltage and transfer them to spice. Also the real JFETs have different Vgs_off and that's not be taken into account in spice.
That's why I suggest adjusting the real unit by ear. However for spice you are best working out the Vgs required to get rds=10k then setting the minimum voltage of the LFO to that number.
QuoteWhich in my conclusion means that the voltage in the output of the trimmer is not fixed, and the LFO only works because of that change. In this case I guess I can conclude that theres more than one feedback loop in this circuit, which seems really hard to understand and calculate..
You need to think of the Vbias source as a Thevenin equivalent circuit. The bias trimpot provides a variable voltage source but the trimpot resistance means the Vbias source has a output impedance (perhaps around 50k ohm). When you probe the trimpot wipe you are probing at the output side of that 50k source impedance. In practice the 50k adds to the 1M resistor in series with the trimpot wiper so it actually ends up having little effect. If you want to check things from theoretical point of view you can replace thr trimpot with a fixed voltage source in series with say 50k but now can probe both sides of the 50k resistor.
Quote from: Rob Strand on September 22, 2020, 06:40:00 PM
Normally you see Rds *increasing* more rapidly as you approach Vgs_off. The drain resistance is,
rds = rds0 / (1 - |Vgs|/|Vp|) ; where rds0 = 1/Yfs0 and is typically around 200 ohms
The resistor (20k to 30k) in parallel with the JFET limits the rise.
Thanks for the insight.
Knowing that I cannot exceed 417 ohm downwards, I did some calculations:
if rds0 (i suppose it's rds on) is 200 (minimum on the 2n5457), within -1.2 and -1.29 vgs (-1.3 Vpinch) I get between 2.5 k and 26 kohm. This now makes sense. Also, for me to get the jFET resistance to 417 ohm (for the notches to not exceed 20kHz), I get -0.676 vgs.
If rds0 is 333 middle case, for me to get the jFET resistance to 417 ohm, vgs is -0.26 V.
Last case is rds on 1khz (max) and I don't even have to worry about the notches, because they won't reach near 20kHz.
So if I get rdson below 417 ohm is when I need to worry, and think about diminishing the voltage span or putting a series resistance with the drain.
Quote
For a typical vintage phaser the JFET rds is probably around 10k ohm to 12k ohms. So if you reverse that calculations that means |Vgs|/|Vp| is 0.98. 2% error of adjustment in Vbias will give |Vgs|/|Vp|=0.96 and that is going to drop rds to 5k ohms. So 2% adjustment error is causing 100% change. It's extremely sensitive.
It's unlikely you will be able to eye-ball the oscilloscope voltage and transfer them to spice. Also the real JFETs have different Vgs_off and that's not be taken into account in spice.
That's why I suggest adjusting the real unit by ear. However for spice you are best working out the Vgs required to get rds=10k then setting the minimum voltage of the LFO to that number.
You say maximum rds? Or do you say rds that is equivalent to the parallel? I didn't get it. However, I understand the idea behind what you're saying. Subtle changes may be = big changes.
I'm thinkin about setting up my circuit in a way that the only preocupation I would have would be the lowest rds possible (which I already calculated as 417 ohm). If the frequency response gives me more than 20k of notch, then I will have a problem and I will want to solve it.
As I'm putting on the sims on this post, I am yes calculating the values of the LFO to give me exactly what I want (and I was able to get 1.1 Volt Span on LFO), but it isn't worth it when I know in real life there will be drastical differences (vgs off not equal tween jfets; yfs not equal tween jfets; no practical way to change resistors in a fast time; having to simulate the phasing part with a voltage source instead of the LFO, etc).
QuoteYou need to think of the Vbias source as a Thevenin equivalent circuit. The bias trimpot provides a variable voltage source but the trimpot resistance means the Vbias source has a output impedance (perhaps around 50k ohm). When you probe the trimpot wipe you are probing at the output side of that 50k source impedance. In practice the 50k adds to the 1M resistor in series with the trimpot wiper so it actually ends up having little effect. If you want to check things from theoretical point of view you can replace thr trimpot with a fixed voltage source in series with say 50k but now can probe both sides of the 50k resistor.
Ok this is great, I just wanted to be able to explain this theoretically. I don't understand the meaning/importance of the impedance here. Well actually maybe I do. The "50k" adds to the 1megaohm, in that way what I dd in my sims above is correct, probed the trimpot with 50k and then to the right of 1mega, which is node Vbias.
However how does this all apply to it's function of the LFO? How could I calculate this? The LFO input is a divider from the LFO out and the Vbias +50k+1mega right? If so, the vbias has a weight of 50k+1mega and the lfo out has a weight of 3.9 mega? And how does the Vbias oscillate?
Tomorrow as soon as I can I will simulate the trimpot as a source with 50k and put results here.
Sorry for all questions but the LFO is tripping me out already.
Quote from: savethewhales on September 22, 2020, 08:04:09 PM
So if I get rdson below 417 ohm is when I need to worry, and think about diminishing the voltage span or putting a series resistance with the drain.
in a normally operating unit you won't be using the full resistive range of the jFET,
and not all the way down to that end either ... so, no need for padding at the drain
the question is, how much relative Cv range is enough here?
with a fixed (300mVpp) control signal swing one would expect the stock P90 LFO circuit to have a much stronger effect operating on lower-Vp devices rather than on higher-Vp ones ... a never-mentioned key player in the variance of the overall response
as a silly/extreme example, if you could somehow manage to find yourself four matched jFETs with their Vp's measuring -0.30 volts you would then theoretically have a stock P90 running at 100% max Depth ... with absolutely no guarantee that it would sound good or useful either
conversely, the P90 LFO can be modded for higher or lower Cv swing ... though, if the common approach (variable loading) is done on the stock circuit then each time the load is adjusted the BIAS trim may need to be re-calibrated in order to regain an even sweep ...
for a more perfect (bias invariant) DEPTH control the whole circuit needs to be re-arranged slightly, with an extra op-amp likely needed ...
Did the sim without the 250k trimpot but with a source and the respective resistance (3.618 V and 62.5k as I had on my circuit), and I was able to look at the voltages that are around the resistors, and the voltage dividing they do:
(https://i.postimg.cc/gnxyxhB8/SIM-23-9-biassource-resist-1.png) (https://postimg.cc/gnxyxhB8)
(https://i.postimg.cc/Vd2qnN3T/SIM-23-9-biassource-resist-2.png) (https://postimg.cc/Vd2qnN3T)
As I can see, the voltage at the 62.5k resistor oscillates a bit, and it's surely making a (really small) difference in the LFO/Vgates. Anyway, I would like to be able to control things to my taste, but it seems I need a little bit of calculations with this (which I've tried but cnnot understand fully).
Quote
in a normally operating unit you won't be using the full resistive range of the jFET,
and not all the way down to that end either ... so, no need for padding at the drain
Yes, with the sims I understood that I don't even want to get to 0 vgs (it would even be bad for me). However, the pad is just to NOT pass that limit resistance, but yes if I desgin the circuit not to pass it, no need for pad (even though I was thinkin would be the simplest).
Quote
the question is, how much relative Cv range is enough here?
with a fixed (300mVpp) control signal swing one would expect the stock P90 LFO circuit to have a much stronger effect operating on lower-Vp devices rather than on higher-Vp ones ... a never-mentioned key player in the variance of the overall response
as a silly/extreme example, if you could somehow manage to find yourself four matched jFETs with their Vp's measuring -0.30 volts you would then theoretically have a stock P90 running at 100% max Depth ... with absolutely no guarantee that it would sound good or useful either
Well, I understand that a CV of vgs-off to more or less 417 ohm rds would be enough for me!
That P90 case is very true and strange. But I was thinkin and I think they do it like that really because the resistance changes so much near the vgs-off point, that you would be "good" having 0.3V p-p span, because your rds would change a lot (maybe not as much as you would want/idealize. Because of this very fact, and some others, is why I am trying to design something slightly different.
Quote
conversely, the P90 LFO can be modded for higher or lower Cv swing ... though, if the common approach (variable loading) is done on the stock circuit then each time the load is adjusted the BIAS trim may need to be re-calibrated in order to regain an even sweep ...
for a more perfect (bias invariant) DEPTH control the whole circuit needs to be re-arranged slightly, with an extra op-amp likely needed ...
When you say variable loading, you mean changing the 1M resistor and the "depth" pot that I have on the schematic? If so, yes I was changing it together with the bias trimmer, because or it was getting an offset upwards or downwards (if I remember correctly), and the solution was to change the bias trimmer at the same time.
This actually started with me trying to reach the lowest voltage of the LFO as being 3.5 Volt (3.5-4.8=-1.3 Volt pinch off), but I haven't made too much of calculations because I don't understand how they would work here. For me it was a matter of trying/error/luck.
It interests me of having a rearrangement of the circuit with an extra op-amp. What did you thought of? Putting an op amp in the out of the 1M ohm resistor? Or for something completely different?
Thanks,
Fred
Quote
You say maximum rds? Or do you say rds that is equivalent to the parallel? I didn't get it.
The values are for the rds of the JFET. The parallel fixed resistor will drop the total resistance.
QuoteHowever how does this all apply to it's function of the LFO? How could I calculate this? The LFO input is a divider from the LFO out and the Vbias +50k+1mega right? If so, the vbias has a weight of 50k+1mega and the lfo out has a weight of 3.9 mega? And how does the Vbias oscillate?
Quote
As I can see, the voltage at the 62.5k resistor oscillates a bit, and it's surely making a (really small) difference in the LFO/Vgates. Anyway, I would like to be able to control things to my taste, but it seems I need a little bit of calculations with this (which I've tried but cnnot understand fully).
You should be able to see why from your simulation. In the simulation the Thevenin voltage is now Vbias and it doesn't fluctuate but the output terminal at the other side of the 62.5k does fluctuate. When you use a trim pot the *open circuit* voltage of the pot is the Vbias in the simulation; that's how you define the Thevenin voltage. However with a trimpot you can see the "internal" Vbias point you only see the output terminal which is the side of the 62.4k that fluctuates.
Yes, the fluctuation is small. Its effect is small because 62.5k is much smaller than 1MEG.
Quote
The values are for the rds of the JFET. The parallel fixed resistor will drop the total resistance.
So you mean the Typical vintage phaser has a parallel resistor of 10-12k?
Quote
You should be able to see why from your simulation. In the simulation the Thevenin voltage is now Vbias and it doesn't fluctuate
Ok
Quote
but the output terminal at the other side of the 62.5k does fluctuate.
Yes!
Quote
When you use a trim pot the *open circuit* voltage of the pot is the Vbias in the simulation;
Okay
Quote
that's how you define the Thevenin voltage. However with a trimpot you can see the "internal" Vbias point you only see the output terminal which is the side of the 62.4k that fluctuates.
Can't, right?
Yes I got that. But the whole question of mine, is how I'm gonna do the calculation, do you understand? Like, how is the voltage coming from the LFO to the 62.5 k resistance? it's something that is bugging me.
Quote
Yes, the fluctuation is small. Its effect is small because 62.5k is much smaller than 1MEG.
Yeah it does make sense actually! I just have to understand how and why the LFO out goes into the 62.5k and the 1Mega.. Is it because the schmitt trigger needs an oscilation? If so, how is this working in the circuit I put above?
QuoteSo you mean the Typical vintage phaser has a parallel resistor of 10-12k?
The *JFET* is 10k to 12k. The circuit will have an additional resistor in parallel with the JFET (typ. 20k to 30k). So the combination will produce a maximum resistance of 8k or so.
QuoteYes I got that. But the whole question of mine, is how I'm gonna do the calculation, do you understand? Like, how is the voltage coming from the LFO to the 62.5 k resistance? it's something that is bugging me.
It's just the Thevenin equivalent circuit of the bias trimpot. It's not a precise value because it depends where the pot is set. The precise method would be to adjust the trimpot then measure the wiper to top-terminal resistance and wiper to bottom-terminal resistance then the Thevenin equivalent impedance is the parallel combination of the two. The ball-park way is to say the pot is 0 ohms at the top and bottom. In the middle it's Rpot / 4 = 250k /4 = 62.5k. So on average it's (62.5k + 0) /2 = 31k.
The whole idea of accounting for the trimpot resistance is that you *know* it has an effect. The effect is small, so throwing in a ball-park estimate just pushes and calculations closer to reality. I do often account for this type of thing because the measurements and calculations don't have a built-in approximation bias.
In the light of not accounting for the JFET's having different Vgs_off it is a small contribution.
QuoteYeah it does make sense actually! I just have to understand how and why the LFO out goes into the 62.5k and the 1Mega.. Is it because the schmitt trigger needs an oscilation? If so, how is this working in the circuit I put above?
The reason is it provides a way for the DC bias and the LFO output to be combined; based on the k factor thing I posted previously. That's what the JFET needs.
The 1M works with the 3M9 resistor to divide down the LFO swing.
You could design the circuit to remove the 1M and 3M9 then design the LFO to have the correct DC offset and LFO swing for the JFETs. If you did that you would find is (if you tried to use a similarly simple circuit),
- The DC bias would vary more when the 9V rail varied. Keep in mind the 9V supply isn't regulated and the these pedals operated off battery, which could vary from say 7V to 10V.
-When you adjusted the DC bias it would affect the LFO duty-cycle and frequency.
As it is the circuit tries to separate the LFO and JFET DC biasing as much as possible. The Vbias from the bias trimpot is mostly determined by the zener voltage, which is relatively independent of the supply. The DC variations from the LFO is kept to a minimum. The guys that designed the LFO designed it like they did because they did consider these factors. From a design point of view, I know the problems that need to be addressed and I can see their design addressed those problems as far a practically possible using fairly common circuit building-blocks. That doesn't mean there aren't other ways to do it!
Quote from: Rob Strand on September 24, 2020, 08:50:09 PM
The *JFET* is 10k to 12k. The circuit will have an additional resistor in parallel with the JFET (typ. 20k to 30k). So the combination will produce a maximum resistance of 8k or so.
Ok!
Quote
It's just the Thevenin equivalent circuit of the bias trimpot. It's not a precise value because it depends where the pot is set. The precise method would be to adjust the trimpot then measure the wiper to top-terminal resistance and wiper to bottom-terminal resistance then the Thevenin equivalent impedance is the parallel combination of the two.
Ok!
QuoteThe ball-park way is to say the pot is 0 ohms at the top and bottom. In the middle it's Rpot / 4 = 250k /4 = 62.5k. So on average it's (62.5k + 0) /2 = 31k.
Wait, why Rpot/4?
QuoteThe whole idea of accounting for the trimpot resistance is that you *know* it has an effect. The effect is small, so throwing in a ball-park estimate just pushes and calculations closer to reality. I do often account for this type of thing because the measurements and calculations don't have a built-in approximation bias.
Hmm okay. It's true. But in my case I want it to be exact. I know the exact caractheristics of the matched jFET's so I wanted to build based on that. That is why I was choosing those values on my circuits on Spice.
Quote
The reason is it provides a way for the DC bias and the LFO output to be combined; based on the k factor thing I posted previously. That's what the JFET needs.
You mean they do an "adder circuit" too? And that's because the LFO needs an "input oscillation" right?
QuoteThe 1M works with the 3M9 resistor to divide down the LFO swing.
Yes.
QuoteYou could design the circuit to remove the 1M and 3M9 then design the LFO to have the correct DC offset and LFO swing for the JFETs. If you did that you would find is (if you tried to use a similarly simple circuit),
- The DC bias would vary more when the 9V rail varied. Keep in mind the 9V supply isn't regulated and the these pedals operated off battery, which could vary from say 7V to 10V.
Hmm why? I would really like to do that, and in this case, use a 9V power supply only. How can I do what youre saying?
Quote-When you adjusted the DC bias it would affect the LFO duty-cycle and frequency.
Hmm.. I would like to see and simulate the circ.
QuoteAs it is the circuit tries to separate the LFO and JFET DC biasing as much as possible. The Vbias from the bias trimpot is mostly determined by the zener voltage, which is relatively independent of the supply.
Yes.
QuoteThe DC variations from the LFO is kept to a minimum. The guys that designed the LFO designed it like they did because they did consider these factors. From a design point of view, I know the problems that need to be addressed and I can see their design addressed those problems as far a practically possible using fairly common circuit building-blocks. That doesn't mean there aren't other ways to do it!
That's where I wanted to get. I wanted to do something quite different and exclusive to the caractheristics of FET's that I have. My problem is, as far as I'm concerned, I need the input to oscillate, as I mentioned before, and I know the P90 circuit has the input on the LFO oscillated by what you explained (even though I don't understand exaaactly how they do it).
Either way i'm starting to think this thread is going too big for casual readers, and I would ask if I can contact you privately.. If so, how?
Thanks and regards.
It's ok fir a thread to be long, as long as it isn't a popcorn thread... :icon_wink:
You can Private Message (PM) by going to the "my messages" and sending messages to any forumite.
I'm sure other people can learn from this thread. Don't worry! ;)
It's still 4 pages long. Still kinda short compared to deadastro's threads... :icon_mrgreen:
Quote from: 11-90-an on September 27, 2020, 03:46:34 AM
It's ok fir a thread to be long, as long as it isn't a popcorn thread... :icon_wink:
You can Private Message (PM) by going to the "my messages" and sending messages to any forumite.
I'm sure other people can learn from this thread. Don't worry! ;)
It's still 4 pages long. Still kinda short compared to deadastro's threads... :icon_mrgreen:
Hahah ok, thanks! I actually tried to contact Rob with PM but not answered yet. I hope to be saying relevant things in this thread!
QuoteWait, why Rpot/4?
If you set the pot to half-way there is Rpot/2 from the wiper to one end and Rpot/2 from the wiper to the other end. Thevenin equivalent resistance is those two in parallel so Rpot /4.
Quote
You mean they do an "adder circuit" too? And that's because the LFO needs an "input oscillation" right?
Yes it does add the DC from the trimpot with the LFO.
QuoteHmm why? I would really like to do that, and in this case, use a 9V power supply only. How can I do what youre saying?
The MXR circuit is already doing that. If you want to see how the circuit performs run you spice simulation with the at 9V and at 7V and look at what happens to the LFO. In this case you might want to reduce the voltage of the zener when at 7V because in reality the zener voltage will drop.
The other thing you can do is compare two designs. You set-up the two circuit to be equivalent at 9V then you change the supply to 7V and look at how the gate voltage is changes. One will change less than the other.
Quote
That's where I wanted to get. I wanted to do something quite different and exclusive to the caractheristics of FET's that I have. My problem is, as far as I'm concerned, I need the input to oscillate, as I mentioned before, and I know the P90 circuit has the input on the LFO oscillated by what you explained (even though I don't understand exaaactly how they do it).
Either way i'm starting to think this thread is going too big for casual readers, and I would ask if I can contact you privately.. If so, how?
Unfortunately coming up with a better design is a whole project in itself. There's many ways to do it. A very simple way to make the circuit tougher against supply variation is simple to regulate the power supply! Ideally you would want to regulate the supply without lowering the headroom of the audio circuits.
First just wanted to say sorry for taking so long, a job appeared and it took me off here for some time.
Quote
If you set the pot to half-way there is Rpot/2 from the wiper to one end and Rpot/2 from the wiper to the other end. Thevenin equivalent resistance is those two in parallel so Rpot /4.
Ok!
Quote
Yes it does add the DC from the trimpot with the LFO.
This is important. I've been searching more and more and by looking about the astable multivibrator circuit, I understand that to get a triangular output, with the circuit of the P90, I HAVE to have some kind of feedback to the input DC, because the triangular wave output will "trigger" the state change of the multivibrator, am I correct?
Now smth I'm thinkin now, is if I use a integrator following the astable multivibrator circuit, in this case an op-amp integrator, I could be able to get a triangular wave without messing with the input DC, does this make any sense?
Quote
The MXR circuit is already doing that. If you want to see how the circuit performs run you spice simulation with the at 9V and at 7V and look at what happens to the LFO. In this case you might want to reduce the voltage of the zener when at 7V because in reality the zener voltage will drop.
I just did the sim, and it gives me a lower voltage span on the LFO... Really it does make sense, as it's changing also the current that goes to the timing cap.. right?
Quote
The other thing you can do is compare two designs. You set-up the two circuit to be equivalent at 9V then you change the supply to 7V and look at how the gate voltage is changes. One will change less than the other.
Wait, I didn't get this, what two designs?
Quote
Unfortunately coming up with a better design is a whole project in itself. There's many ways to do it. A very simple way to make the circuit tougher against supply variation is simple to regulate the power supply! Ideally you would want to regulate the supply without lowering the headroom of the audio circuits.
Of course, it makes sense. I brought up an idea above, that I think would work.. I'm going to simulate it as soon as I can.
Btw, I'm going to use a 9V power supply (the one that connects to the wall hahah) so I think it would be "regulated", and when you talk about the headroom I can only think about the usual 100mV peak headroom of the jFET's... It would block any attempt of mine to get more headroom, I'm guessing.
Hey guys,
So, I'm trying to experiment with this LFO circuit, that in theory can give me a triangular LFO without all that DC bias stuff:
(https://i.postimg.cc/94hnnpWh/Imagem1.png) (https://postimg.cc/94hnnpWh)
However, when I simulate it on LTSpice, with the circuit below:
(https://i.postimg.cc/p5hCTh2C/LFO.png) (https://postimg.cc/p5hCTh2C)
I get no square nor triangular wave on the output, just like I will show:
(https://i.postimg.cc/G8NPZLky/LFO2.png) (https://postimg.cc/G8NPZLky)
This is happening no matter what initial condition I put/don't put.. Also I've changed the Vcc values, changed the reference to a bigger voltage and nothing.. Could I be doing something wrong or is it not supposed to work?
Later I've tried to sim another triangular LFO circuit, as following:
(https://i.postimg.cc/D8c6zTht/LFO3.png) (https://postimg.cc/D8c6zTht)
And yet again I can't seem to get a good transient response.. even with the initial times on.. wth! Can somebody help please?
Smth is going on and I don't know what.
QuoteAnd yet again I can't seem to get a good transient response.. even with the initial times on.. wth! Can somebody help please?
Smth is going on and I don't know what.
Have a look at the schematics for the Boss CE-2 Chorus or the Boss BF-2 Flanger and see if you can find your mistake.
Quote
Have a look at the schematics for the Boss CE-2 Chorus or the Boss BF-2 Flanger and see if you can find your mistake.
Looking at the circuits, I'm afraid I couldn't find the mistakes I've done... Actually, I've taken the circuits I simulated from sites which explain them, the sites are:
https://kassu2000.blogspot.com/2015/10/variable-waveshape-lfo.html?m=1
And
https://www.google.com/amp/s/synthnerd.wordpress.com/2018/12/31/synth-diy-the-relaxation-lfo/amp/
Now this last one even has a online simulation, where I could change the values of resistors and see what happens to the circuit. I basically did it just like it is on the website, and nothing.. I can seem to understand what goes on, so as I'm going to use an oscilloscope today, maybe I will see if I can make the circuit oscillate..
It's just I wanted to make an oscillator without the Vbias mambo jambo, or in other words, something fixed, derived from an astable multivibrator (as this last one is) as far as I'm concerned
Compare your circuit to this, and see if you can see the problem,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
Quote from: Rob Strand on September 30, 2020, 05:54:34 AM
Compare your circuit to this, and see if you can see the problem,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
Sooo.. Virtual ground? If so, I already tried to do with and without, and nothing...
Yes, virtual ground, because it is a single supply. Another thing is I think you entered 220K into the part designator field (ie. R1, R2, etc) instead of the value field. Which is currently 1K not 220K.
Quote from: Rob Strand on September 30, 2020, 06:43:02 AM
Yes, virtual ground, because it is a single supple. Another thing is I think you entered 220K into the part designator field (ie. R1, R2, etc) instead of the value field. Which is current 1K not 220K.
Yes and yes. I was dumb.
Was putting 15v and 0V for supplies, while not using virtual ground on the inverting/non-inverting...
I am now beside a oscilloscope and I'm able to tell what's the differences bewteen the circuits that we were just talking (with and without virtualground/with and without dual supply, etc. ).
Based on this site: http://www.falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+188.4969023643409+72+10+50%0Aa+720+320+848+320+8+14+-14+1000000+-4.775034505202351+-5.025650017083231+100000%0Aw+720+304+720+240+0%0Ar+720+240+784+240+0+10000%0Aw+848+240+848+320+0%0Ar+848+384+848+320+0+100000%0Aw+720+336+720+384+0%0Ar+848+384+848+448+0+56000%0Ag+848+448+848+464+0%0Ac+656+336+656+240+0+0.0000022+4.775034505202351%0Ag+656+336+656+352+0%0AO+1120+304+1184+304+0%0A174+784+240+832+272+0+1000000+0.7475+LFO+Rate%0Aw+784+240+784+272+0%0Aw+784+272+816+272+0%0Ax+790+209+850+212+4+14+LFO%5CsRate%0Aa+992+304+1072+304+8+14+-14+1000000+-4.7749867553347976+-4.775034505202351+100000%0Ar+1072+304+1120+304+0+1000%0Aw+992+288+992+240+0%0Aw+992+240+1072+240+0%0Aw+1072+240+1072+304+0%0AS+992+320+912+320+0+1+false+0+2%0Aw+720+384+848+384+2%0Aw+656+240+720+240+2%0Aw+720+240+720+176+0%0Aw+720+176+912+176+0%0Aw+912+176+912+304+0%0Aw+848+384+912+384+0%0Aw+912+336+912+384+0%0Ax+930+358+975+361+4+14+Square%0Ax+927+290+977+293+4+14+Triangle%0Ax+976+169+1174+172+4+12+Approx%5Cs0.3%5Csto%5Cs30Hz%5Cswith%5Csthese%5Csvalues%0Ax+1009+142+1135+145+4+24+Simple%5CsLFO%0Ax+806+231+822+234+4+12+1M%0Ax+943+206+1203+209+4+12+In%5Csthis%5Csexample,%5Cssupply%5Csrails%5Csare%5Cs%5Cp/-15V%5Csand%5CsGND%0Aw+1072+304+1072+352+0%0Ar+1072+352+1120+352+0+1000%0Ax+1133+356+1313+359+4+12+add%5Csas%5Csmany%5Csoutputs%5Csas%5Csyou%5Csneed%0Ax+867+443+1247+446+4+12+Adjust%5Csthe%5Csratio%5Csof%5Csthese%5Cstwo%5Csresistors%5Csto%5Csset%5Csthe%5Csflip%5Cslevel%5Csof%5Csthe%5Csoscillator%0Ao+10+1024+0+4362+10+0.00009765625+0+1%0A
Here it is the circuit with +-15 Volt and ground on the non inverting:
(https://i.postimg.cc/7Jv3fk4v/TEK0000-2.png) (https://postimg.cc/7Jv3fk4v)
And here it is the circuit with the battery and the Vreference of around 4.8 Volt (I moved it down to be centralized, but the values can be seen down low (minimo=minimum, and maximo=maximum).
(https://i.postimg.cc/qNB8twP7/TEK0000-3.png) (https://postimg.cc/qNB8twP7)
As I can see, I can use a voltage reference to make a DC offset, and I can make the span lower or higher for my taste, however I can't seem to find a solution to put this thing going between 3.5 and 4.6 Volt... With a Zener I feel like I would be badly served because mine is 5.1 Volt.. Is there any way I can get around that? Maybe doing a voltage divider from the Zener just like the P90, but without the whole DC bias stuff?
Thanks in advance.
QuoteAs I can see, I can use a voltage reference to make a DC offset, and I can make the span lower or higher for my taste, however I can't seem to find a solution to put this thing going between 3.5 and 4.6 Volt... With a Zener I feel like I would be badly served because mine is 5.1 Volt.. Is there any way I can get around that? Maybe doing a voltage divider from the Zener just like the P90, but without the whole DC bias stuff?
The 100k and 56k set the Schmitt trigger thresholds.
For you +/-15V case in the link:
- Supply +/- 15V
- Opamp output swing about 1V less than power rails, so +/-14V
- Schmitt trigger voltages are the voltages at the out of the 56k + 100k divider
Vt = +/- 14 * 56k / (100k + 56k) = +/-5.02V ; that agrees with you simulation.
A slightly different way to look at it is to separate the DC level and the *change* in the output level.
The input to the divider swings -14V to 14V, a total change of 28V.
The change in voltage at the output of the divider is 28V * 56k / (100k + 56k) = 10.05V ; which agrees with 2x5.02V
The change in the Schmitt trigger sets the change in threshold and also sets the change in the peak to peak output of the triangle wave.
For your 9V case with DC offset,
You currently have 3.68V to 6.16V which is a change of 2.48V
But you want 3.5V to 4.6V, which is a change of 2.1V
You want to reduce the change by a factor of 2.1/2.48 = 0.847.
The way to reduce the swing at the output is the modify the Schmitt trigger levels. You want to reduce them
If we go back to your +/- 15V simulation.
The 100k + 56k divider sets the Schmitt trigger levels. To reduce Schmit trigger them we could for example decrease the 56k.
If you set the 56k to 43.7k the voltage change at the output of the divider is,
28V * 43.7k / (43.7k + 100k) = 8.51V
This reduces the swing by a factor of 8.51/10.05 = 0.85.
If you modity the value in you falstad similation you will see it works.
If you use these new values on you 9V circuit you will find the change in the output is close to what you want. It will be a bit low because the opamp doesn't swing to the full supply and this affects a 9V circuit more than a +/-15V circuit. So you may need in increase the value from 43.7k.
Once you get the change in the output correct you can use the DC offset to shift it so the actual voltages are where you want them.
The way I've describe it above is to take something that is nearly correct and tweak it. You can actually calculate the required divider ratio and the 43.7k resistor from maths without ever build a trial circuit. Look up how to calculate Schmitt trigger levels. I think I already explained this.
I mentioned this before, when you use the DC offset you will find the output duty cycle changes. The time to rise-up is no longer the same as the time to fall-down. That's another reason why the MXR pedal separates the DC bias and the LFO.
As soon as I can I will answer this accordingly, but for now I just wanted to say I managed to get the 3.5-4.6, volt span, by having 18k to ground and 100k making a divider with it (which gives me 1.1 volt span), and then I used 4.8 V from the zener (5.1 V zener with a 3.3k resistor) and then at the end of the LFO I used an op amp to buffer plus a resistance dividing at the end with 56k to ground and 10k.
Anyway, I'm getting the results good but the response of the triangle gets a flatter edge sometimes and I don't know if it is wiring problems or what.. When I can I 'll show you.
So,
For this exact circuit (except for the zener that is different):
(https://i.postimg.cc/QBT5HtfS/circuito-integrador-1-10-2020.png) (https://postimg.cc/QBT5HtfS)
I get this transient sim (clean as F):
(https://i.postimg.cc/tsV7zcF4/sim-circ-integrador-1-10.png) (https://postimg.cc/tsV7zcF4)
Now, these are the results I'm getting out of the testing on oscilloscope, and I'm kinda worried not knowing what to do or what causes this (notice that I already checked every single point and changed wires everysinglewhere, but none changed) -
Output:
(https://i.postimg.cc/TL5k2fbX/TEK0007.png) (https://postimg.cc/TL5k2fbX)
Output of the capacitor C2:
(https://i.postimg.cc/D4dPmZyR/TEK0006.png) (https://postimg.cc/D4dPmZyR)
non inverting input of the first op-amp:
(https://i.postimg.cc/BjyYrj8C/TEK0005.png) (https://postimg.cc/BjyYrj8C)
Output of the op-amp (could be better):
(https://i.postimg.cc/Z07r71v8/TEK0002-3.png) (https://postimg.cc/Z07r71v8)
Evidently The square output on the non inverting is not reeeally a square wave, but I don't think that is supposed to be causing the output """triangle""" that I'm having.. Can somebody help me please?
Thanks.
Quote from: Rob Strand on September 30, 2020, 08:28:35 PM
The 100k and 56k set the Schmitt trigger thresholds...
...For your 9V case with DC offset,
You currently have 3.68V to 6.16V which is a change of 2.48V
True! I actually was doing that yesterday and I found ot that with the 9V single supply with a voltage reference on the virtual ground, I was needing a 18k resistor (the closest to real values) to get my LFO as I wanted.
Quote
But you want 3.5V to 4.6V, which is a change of 2.1V...
...If you modity the value in you falstad similation you will see it works.
Just one thing, the change I want is 1.1 V not 2.1 (3.5 to 4.6).
However, yeah, of course, I did exactly what you're sayng, changed values on the virtual simulation of the site and saw how they went and then did math to find the exact values.
Quote
If you use these new values on you 9V circuit...
...That's another reason why the MXR pedal separates the DC bias and the LFO.
Exactly! You already explained the schmitt trigger levels (and I learned how to do it on the internet at the same time). Any way it does make sense that it affects most the 9V single supply.
My duty cycle as I put on the post above, is really messed up.. Don't really know what to do now..
When you say separating the DC bias and the LFO you mean those big 3m9 and 1m resistors?
QuoteEvidently The square output on the non inverting is not reeeally a square wave, but I don't think that is supposed to be causing the output """triangle""" that I'm having.. Can somebody help me please?
The 'tilt' on the square-wave is due to the AC coupling on the oscilloscope, not the circuit.
QuoteJust one thing, the change I want is 1.1 V not 2.1 (3.5 to 4.6).
There is a problem with trying to get down to 1V directly from the opamp. Some opamps don't work when the inputs are too close to the either the positive or negative supply rail (or both). It's called the common-mode range in the opamp datasheet. For the Schmitt trigger to work the opamps have to operate with their common mode -range. For many opamps the lower limit is 2V from the negative rail so that means trying to get a 1.1V threshold won't work. One option is to use a different opamp, one that has a common-mode range that is closer to the negative rail. The other way is to use a circuit similar to the 1M + 3.9M used on the MXR phase. In this case the 1M side can be tied to a low voltage to lower and shift the DC point down at the output. The LFO is then designed with higher voltage levels, which are within the opamp's common mode-range.
The take home message is when you change circuits you need to be aware of all the hidden factors. The original circuit might work but a modified circuit might not because you haven't considered all the factors affecting the performance. In this case it's the common mode range. That doesn't always mean it can't be done. You can change the opamp to a different type, one that has a common-voltage closer to zero.
QuoteWhen you say separating the DC bias and the LFO you mean those big 3m9 and 1m resistors?
Yes.
QuoteMy duty cycle as I put on the post above, is really messed up.. Don't really know what to do now..
It's not straight forward to fix, especially when the LFO frequency needs to vary with a pot.
The problem is this:
When you lower the Scmitt-trigger levels the timing cap voltage is much lower (say 3V). When the cap is discharging, it discharges towards 0V from 3V.. However the cap charges, it charges towards about 9V, that means there is (9V-3V) = 6V across the timing resistor. The capacitor will charge-up quicker than it can discharge. So by nature the rising part will be shortened.
The root of the problem is the opamp output is swinging to approx 9V. If you wanter to solve this problem you would need to limit the output swing of the opamp. So tat can be done by reducing the supply voltage. Or you can feed the output to a zener diode with a series resistor to clamp the output voltage. There's many ways to do it.
I believe original idea was to make the simplify the circuit by trying to get the DC bias directly off the LFO, so you could remove the bias pot (and 1M resistor). However that's caused a whole lot of new problems and to fix it you have to add more part's than you saved. That's why people end-up using the MXR type circuit!
Quote
The 'tilt' on the square-wave is due to the AC coupling on the oscilloscope, not the circuit....
...There is a problem with trying to get down to 1V directly from the opamp.
...It's not straight forward to fix, especially when the LFO frequency needs to vary with a pot.
...That's why people end-up using the MXR type circuit!
First sorry being late, I have been crazy working on the physical tests of the circuit, which are only possible when I go to my college, which is far from home, you get the scene.. Anyway I have good news.
I have an idea of having messed with the ground after that and being able to keep the output triangle without the tilt..
Either way I wasn't satisfied and went to do another circuit, based on the first on I put here.
With this one, I was able to get the voltage range that I wanted, as well as having a nice triangle on the output without failing on rise/fall etc.
I'm not yet sure if it really was cables problems/ground problems/smth else. All I know is it worked and I even put a potentiometer of 470k to determine the ranges. The maximum value gives me less range and the minimum value is the opposite.
Here's the circuit:
(https://i.postimg.cc/McCpSfk2/integrator-circuit.png) (https://postimg.cc/McCpSfk2)
I got the output out of a voltage divider to pull down the DC offset.
Here are the image taken from the oscilloscope at maximum and minimum range, respectively:
(https://i.postimg.cc/qt3CyT4r/TEK0005-2.png) (https://postimg.cc/qt3CyT4r)
(https://i.postimg.cc/rKw0gWMQ/TEK0004-2.png) (https://postimg.cc/rKw0gWMQ)
I still haven't decided what frequency range I will want on the LFO, but I believe between 0.3 and 8 Hz will be good and "do-able" with this circuit (500k pot on the place of R4).
I read everything that you said Rob, for what you said I thank you a lot.
If problems happen with my LFO I'll be sure to start thnking and simulating what you told me. There's some reason why they do it like MXR.. I had to go this far to understand it, but if had not come here, I would still not be understanding a single thing of the P90 LFO.
...
As for the main circuit (from the input to the summing of the wet+dry signals), I unfortunately am having headaches because it just won't work no matter what I do. I imagine it has to do with cables or smth. I spent the whole day trying to understand the why's, without having any answer...
Before what's down here, Wanted to be clear that the simulations are all ocurring accordingly, and nice (even if I take off some elements which I will mention below).
The circuit is down here:
(https://i.postimg.cc/D4V6Lgtj/circuito-Rob-Str.png) (https://postimg.cc/D4V6Lgtj)
However I haven't build the whole circuit on bread, I left out two stages of phase shifting (just to see what one would give me) and I left out the output op amp (because I didn't really want gain).
Is there any way that I can make the circuit work by testing different parts of each time? And what parts? Because like if I leave only one all pass filter, I have no change on the output, and I wouldn't know if it's doing correctly..
I'm just really lost and already thinking on the possibility of having to buy the pcb without really knowing that the circuits works.
Regards, Fred
QuoteAnyway I have good news.
With this one, I was able to get the voltage range that I wanted, as well as having a nice triangle on the output without failing on rise/fall etc.
I'm not yet sure if it really was cables problems/ground problems/smth else. All I know is it worked and I even put a potentiometer of 470k to determine the ranges. The maximum value gives me less range and the minimum value is the opposite.
Here's the circuit:
I got the output out of a voltage divider to pull down the DC offset.
You did well. That way should work.
If you put in JFETs with larger VP and adjust the divider to set the bias the LFO output at the divider will get smaller. The larger VP JFETs actually need bigger LFO swing to get the same resistance range.. The MXR keeps the LFO output constant, which still isn't correct.
QuoteAs for the main circuit (from the input to the summing of the wet+dry signals), I unfortunately am having headaches because it just won't work no matter what I do. I imagine it has to do with cables or smth. I spent the whole day trying to understand the why's, without having any answer...
Before what's down here, Wanted to be clear that the simulations are all ocurring accordingly, and nice (even if I take off some elements which I will mention below).
However I haven't build the whole circuit on bread, I left out two stages of phase shifting (just to see what one would give me) and I left out the output op amp (because I didn't really want gain).
OK let me get this straight. The sims look OK but the actual breadboard isn't working
Measuring the DC voltages at the output of all the opamps is a good start to identifying problems. The DC voltage should be Vref.
QuoteIs there any way that I can make the circuit work by testing different parts of each time? And what parts? Because like if I leave only one all pass filter, I have no change on the output, and I wouldn't know if it's doing correctly..
Yes, the only thing you have to be careful about is when you separate part of the circuit it might not work because it needed the DC voltage of the previous stage to bias the opamps correctly. Also if you connect a signal generator without *adding* a coupling cap to the input it will connect that input to 0V in a DC-sense and complete stuff-up the biasing. If you are careful about those aspects you can easily separate the parts. If you don't do it right you will have more headaches than you already have.
Another approach would be to replace the JFETs withs with fixed resistors, say 3k3 to 4k7. For two stages that will put the notch at 1kHz. Put a 3kHz signal on the input. One important thing is you might need to keep the signal level to about 100mVpk otherwise the JFETs could distort the signal. Connect channel 1 of the oscilloscope to the input signal. Then use channel 2 to look at the outputs of the opamps from left to right on the schematic. Compare the level and phase of the signal.
If you want to see what you expect you can actually set-up the same circuit in LTspice.
To check the mixer you try lifting disconnect the 150k to the last all-pass filter and see the output of the mixer is just the inverse of the input signal.. Then replace the 150k and disconnect the 150k to the input buffer and you should see the output of the mixer is the inverse of the signal at the last all-pass filter.
Connect both 150ks and sweep the signal generator frequency and see if you can find the notch at 1kHz.
If you get that far you know the signal is passing through all the stages correctly.
Put the JFETs back in. Connect the gate to a trimpot so you can adjust the bias to get the notch at 1kHz. Measure the Vgs voltage to make sure it corresponds to about rdson = 3.3k ohm. Check against the LT spice sim.
Finally put back you LFO. If you have trouble now you know it's not the opamps or the JFETs. It probably something to do with the DC level from the LFO.
Quote from: Rob Strand on October 03, 2020, 07:33:51 PM
You did well. That way should work...
... The MXR keeps the LFO output constant, which still isn't correct.
QuoteOK let me get this straight. The sims look OK but the actual breadboard isn't working...
... It probably something to do with the DC level from the LFO.
Wow I don't even know how to thank you. For now, THANK YOU!
About the last sentence, I didn't connect the LFO to the main circuit (because the analyser can't do a frequency response with the LFO varying), so I put a fixed voltage coming from the zener divider going to the gates.
Another thing is, what is that of the capacitors on the input? I should connect them right after the input signal, and then in series with the main circuit?
I'm going to college right now to use and test the circuit, so I'll be putting updates here regarding this.
Later
Right off the bat, I was getting a distorted sinusoid on the input, not even the output..
Actually the output "seemed" better because the scale was bigger.
the circuit I started testing is this:
(https://i.postimg.cc/QVkScKpM/circ-test-04-10-Rob.png) (https://postimg.cc/QVkScKpM)
And the input wave is shown as follows:
(https://i.postimg.cc/McMj5NND/TEK0000-7.png) (https://postimg.cc/McMj5NND)
Could it be that it's because I didn't put a capacitor on the input?
*EDIT*: Managed to get nice and clean waves. The problem was the amplitude of minus than 100mVp, it gave me too much noise.. (the following has 1V peak on input):
(https://i.postimg.cc/9RC3BRQY/TEK0001-5.png) (https://postimg.cc/9RC3BRQY)
Good news here,
I was able to build the circuit on bread and see it work (with resistors on place of the FET's and with the FET's). First I build with one fiter only to measure the DC voltages. As I saw 4.8V on the op-amp outputs, I went to build one more filter to be able to make the notch. When I saw 4.8 Volts on outputs of this new op amp after building (after this circuit:)
(https://i.postimg.cc/V5vVnPFS/circ-test.png) (https://postimg.cc/V5vVnPFS)
, I decided to go and see it on the oscilloscope:
(https://i.postimg.cc/4n1z1WXr/Test-FET-s-3.png) (https://postimg.cc/4n1z1WXr)
With resistors (both 47k):
(https://i.postimg.cc/DmRBGJZD/teste-2filtros-allpass-2.png) (https://postimg.cc/DmRBGJZD)
I had a cut frequency of 213 Hz, just like I calculated (with the equation "fnotch=(tan(90/2))/(2.pi.c.rparallel)", just like the one that is shown on electrosmash explanation. Actually it's important to say that the 90º is in each filter, which leads to 90+90=180 (as I build it with only 2 all pass filters, aka 1 stage).
After seeing it had worked with resistors , went on and put the jFET's, but alternatively to putting pot's, I simply made a divider to have -1.3 Vpinch off (which is what I had measured).
Here are some screenshots of the sims on the osciloscope:
(https://i.postimg.cc/8F1GLkw8/Test-FET-s-5.png) (https://postimg.cc/8F1GLkw8)
(https://i.postimg.cc/zbV9kygQ/Test-FET-s-6.png) (https://postimg.cc/zbV9kygQ)
What I wanted now was to use a pair of FET's (reportedly -1.3 Vpinch off) with Vgs on pinch and on 0V and see on Audio precision what the frequency response was.
-1.3 vgs
notch around 173 hertz
Which is equal to rds=aproximattely 100kohm
(https://i.postimg.cc/Wd1SZQrW/teste-JFET-3-5-Volt-Gate.png) (https://postimg.cc/Wd1SZQrW)
0 vgs:
notch around 22khz
Which is equal to rds=150 ohm
(https://i.postimg.cc/PvdVRNph/teste-JFET-4-8-Volt-Gate.png) (https://postimg.cc/PvdVRNph)
Now the same process substituing for other 2 FET's with measured vgs of -1.3
-1.3 vgs
notch around 170 hertz
Which is equal to rds=aproximattely 100kohm
(https://i.postimg.cc/LhTm61Vt/teste-JFET-2-3-5-Volt-Gate.png) (https://postimg.cc/LhTm61Vt)
0 vgs:
notch around 23.5khz
Which is equal to rds=150 ohm
(https://i.postimg.cc/G8R1bL8g/teste-JFET-2-4-8-Volt-Gate.png) (https://postimg.cc/G8R1bL8g)
All of this was very important for me to do because I could see that the results of rds were not even close to what I measured (after all the methods used I got around 320 ohms), what means that only by doing this type of test was I able to see how my recent bought FET's responded.
I didn't even had much time from the moment I made the circuit work, so I couldn't test exactly if the vpinch-off of those FET's was really -1.3V, or if it was different too (but making the calculations it seemed correct).
Now besides all of that, and after seeing the images, I wanted to know what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)? I made calculations to not lose audio frequencies, and that counts to the input DC filter (with the capacitor). Did I calculated wrong? The resistor R3 doesn't enter on the equaton right? Or am I missing something?
Oh and btw, the 6dB gain overall is desired (summing amplifier with 150k on the negative feedback).
> what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)?
C8.
Quote*EDIT*: Managed to get nice and clean waves. The problem was the amplitude of minus than 100mVp, it gave me too much noise.. (the following has 1V peak on input):
OK no problem. Grounding the metal plate on the breadboard can help reduce noise. Also use shielded cables, and keep the cables short. It's good to know how to reduce external noise because sometimes you don't have the luxury to increase the input level.
QuoteAll of this was very important for me to do because I could see that the results of rds were not even close to what I measured (after all the methods used I got around 320 ohms), what means that only by doing this type of test was I able to see how my recent bought FET's responded.
For you case of 47k in parallel with 24k, I get 213Hz for the notch. So all resistor test looks OK.
For the JFETs, I'm not sure what is happen here either.
When you test with JFETs the signal level can affect the results, especially if you are driving more than about 500mV peak. The JFETs are non-linear. (I can't say this is the cause in your case.)
For the low resistance test, if the way to set-up the trimpot shorts the gate and source then that test should be a good indication of the JFET resistance.
For the Vgs = -1.3V test. This region is very sensitive to the Vgs voltage. I wouldn't worry about the results.
What you should do is a test with Vgs set to around -Vp/2.
The other thing is to verify the JFET resistance with a divider circuit for the Vgs=0 and Vgs = -Vp/2 cases.
It's worthwhile using an oscillator an oscilloscope to find where the notches are manually. Try different signal level to see what affect the signal level has on the notch. That gives you a good idea where is should be. If the Audio precision test unit gives different results the test signal level could be affecting the results. Signal distortion, caused by driving the JFETs too hard, can sometimes cause test systems to produce incorrect results.
QuoteI didn't even had much time from the moment I made the circuit work, so I couldn't test exactly if the vpinch-off of those FET's was really -1.3V, or if it was different too (but making the calculations it seemed correct).
Probably worthwhile since it can affect the results.
QuoteNow besides all of that, and after seeing the images, I wanted to know what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)? I made calculations to not lose audio frequencies, and that count
The problem is probably caused by the 10nF output capacitor. I'm seeing roughly -3dB at 60Hz, and that means you only need about 270k load. For a test set-up you want to make sure the load can't affect the results. Use a big one cap for testing like 1uF.
One other thing I noticed. You always got 5dB and not 6dB for the maximum gain. The 33k and 470k is forming a divider which loses -0.6dB. If you dropped the 33k to 4.7k it would reduce the loss.
Quote from: Rob Strand on October 04, 2020, 08:39:37 PM
OK no problem... If you dropped the 33k to 4.7k it would reduce the loss.
One thing good about all this is (just like some one said on this forum,), is that you always make me look for more, and that is beyond good..
Some points before I do the testings today:
Input never passed 100mV peak because of the FET's limit.
I tried to see the extremes of the FET's to see how they responded and the maxium/minimum resistamces.
Anyway in the 0 VGS, I put thesame voltage on the Gate and the Source, namely 4.8 V.
I will do the jFET test on -Vp/2 to see how it reacts.
One thing: how can I know where the notches are manually? By changing the frequency on the input sine right?
Will also check for the gain of circ and the cutoff frequencies of the high passes.
QuoteInput never passed 100mV peak because of the FET's limit.
100mV pk is very conservative. The error due to non-linearity rises slowly with the peak. I wouldn't be too worried about 200mV pk if you had to go that high. However above 500mV pk you would expect some effect on the measurements (maybe 10%).
QuoteI tried to see the extremes of the FET's to see how they responded and the maxium/minimum resistamces.
Anyway in the 0 VGS, I put thesame voltage on the Gate and the Source, namely 4.8 V.
I will do the jFET test on -Vp/2 to see how it reacts.
The main thing is to try to work out why you measurements are off from the theory. If you can build a simple divider and measure rds for those Vgs values it should give you an idea what to expect when you put the same JFET with the same voltage into the phaser circuit.
Something weird would be going in if the divider looked like one rds value and the divider looked like another when Vgs was set to the same value.
QuoteOne thing: how can I know where the notches are manually? By changing the frequency on the input sine right?
Yes. Set the level and look at the oscilloscope for the minimum.
QuoteWill also check for the gain of circ and the cutoff frequencies of the high passes.
If you change the output cap I'm sure you will be OK. Of course you can try to match-up the -3dB point with theory based on the cap value and the load resistance.
Quote100mV pk is very conservative. The error due to non-linearity rises slowly with the peak. I wouldn't be too worried about 200mV pk if you had to go that high. However above 500mV pk you would expect some effect on the measurements (maybe 10%).
OK!
Quote
The main thing is to try to work out why you measurements are off from the theory. If you can build a simple divider and measure rds for those Vgs values it should give you an idea what to expect when you put the same JFET with the same voltage into the phaser circuit.
Something weird would be going in if the divider looked like one rds value and the divider looked like another when Vgs was set to the same value.
I am testing right now with a potentiometer as a voltage divider. On maximum (4.8V) is giving me 12.75kHz notch now (?) and minimum is giving me 157 Hz. This is giving me rdson=265.6 ohm for the maximum. Not bad.
Doing a very slow turn I found out the Vpinch off that I calculated is almost right. I am getting -1.33 Volt.
QuoteIf you change the output cap I'm sure you will be OK. Of course you can try to match-up the -3dB point with theory based on the cap value and the load resistance.
Worked! Thank you and PRR!
First things first:
By doing a simulation on Matlab, I could see that the maximum frequency that a 1 stage phaser needs to have, for me, is 8261.7 Hz (417 ohm on rds, which gives me more than 20kHz when I use 2 stages). So, that's what I searched for with the audio precision unit and messing with a potentiometer to the gates of the FET's.
I found out that with the 2 first testing FET's I couldn't pass the 4.27Volt mark and with the 2 last testing FET's I couldn't pass the 4.2 Volt mark.
After that, I tested the 2x pair of FET's to their maximum and miinimum values of equivalent resistance.
(this site doesn't accept the type of file that the APX exported)
With 0 V on the gate :
- Pair 1 of FET's:
160 Hz notch
- Pair 2 of FET's:
160 Hz notch
With 4.8 V on the gate :
- Pair 1 of FET's:
21,625khz notch
- Pair 2 of FET's:
21 khz notch
This means that the minimum resistance lies around 175 ohm if I'm not mistaken, and that doesn't match with my early measurements. No problem because I wouldn't even need to use less then 417 ohm rds.
Then, I tested to see in what EXACT voltage on the gate would the FIRST change on the first notch be:
- Pair 1 of FET's:
3.41 Volt
- Pair 2 of FET's:
3.47 V
With that I conclude that my early measurements of VGS were somewhat close (I measured -1.3 V generally, and here I got around -1.33 to -1.39 V).
Also, I tested both pair of FET''s and I slowly increased the voltage on the input to see how they reacted: I reached 1Vpeak without any change on the waveform/anything suspicious. Anyway I decided to stop there.
I managed to confirm the limits which I can use with my LFO, which are 3.4 to 4.2 Volt on the Gates.
That gives me 0.8 Volt range on the LFO.
Realizing that the less the range, the worst is the "triangular wave", in general.. Can someone explain to me why this happens, and how can I fix it?
Before I had this:
(https://i.postimg.cc/6486yQZJ/TEK0002-5.jpg) (https://postimg.cc/6486yQZJ)
But by changing the components to get less range than what I had, what I ended up is with this:
(https://i.postimg.cc/kVjdKmqn/TEK0009.jpg) (https://postimg.cc/kVjdKmqn)
Now what happens is that this is the final LFO circuit I designed:
(https://i.postimg.cc/JDGtBKw2/circ-LFO-ultimo.jpg) (https://postimg.cc/JDGtBKw2)
Where R1 is a 470k pot, R5 is also a pot, and C1 is 100uF (this one to me is smelling like trouble, but it's what I found out to be the best).
In practice I get around 0.3 to 8 Hz of LFO (while the higher frequency gives me a wave that is very distorted, just like shown above), while on theory the results give a bit different taste.
And actually the DC level is not yet set right (maybe it is, but I haven't tested the DC level on the osiloscope yet).
The problem is the square wave (on the input) is feeding through the integrator. It's like the two parts of the triangle separate.
Many possible causes, you would need to probe the circuit to find something,
- Vref is shifting when the Schmitt-trigger changes states
- Could be related to the 100uF cap.
Are you using a non-polar cap or an electrolytic?
- High impedance in the ground wires or bad ground connections.
See how two electrolytics are placed back to back to emulate (C27 & C28) non-polar cap (of half the value),
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
Quote from: Rob Strand on October 05, 2020, 07:23:33 PM
The problem is the square wave (on the input) is feeding through the integrator. It's like the two parts of the triangle separate.
exactly! But like, how can I avoid it...
Quote
Many possible causes, you would need to probe the circuit to find something,
- Vref is shifting when the Schmitt-trigger changes states
- Could be related to the 100uF cap.
Are you using a non-polar cap or an electrolytic?
- High impedance in the ground wires or bad ground connections.
When I can I will check it (but how can I probe if it changes all the time?).
I'm curious to see how vref behaves with this.. It's very possible that it's shifting.
The 100 uF cap was put there after me getting the image I put above, and it's electrolytic (the minus is on the output of the first op amp)
About the ground wires, how can I make the impedances smaller then?
And for the ground, I checked it like 20 times (because last time I had problems with it) and nothing...
[/quote]
Quote
See how two electrolytics are placed back to back to emulate (C27 & C28) non-polar cap (of half the value),
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
Pretty interesting! But why not use only one non-polar cap? hahah
Quoteexactly! But like, how can I avoid it...
It's more a case of finding the cause.
QuoteWhen I can I will check it (but how can I probe if it changes all the time?).
Use the oscilloscope. Find a place in the circuit which shows a small square-wave at the LFO frequency Start investing the cause.
QuoteI'm curious to see how vref behaves with this.. It's very possible that it's shifting.
At this point it is quite possible. The power rail fluctuating can also cause it (the zener should remove most of it).
QuoteThe 100 uF cap was put there after me getting the image I put above, and it's electrolytic (the minus is on the output of the first op amp)
Ok an electrolytic probably isn't the right thing for the job there. It could be causing the problem.
QuoteAbout the ground wires, how can I make the impedances smaller then?
And for the ground, I checked it like 20 times (because last time I had problems with it) and nothing...
Good chance it's not the problem then.
QuotePretty interesting! But why not use only one non-polar cap? hahah
When that circuit came out large bipolars weren't so popular so the designers chose to make their own.
It's probably worth your while changing the cap from a single electrolytic to a non-polar, or doing the two cap thing if you don't have the bipolar caps on hand.
Quote
Use the oscilloscope. Find a place in the circuit which shows a small square-wave at the LFO frequency Start investing the cause.
Nice.. Will do it when I am able to use an oscilloscope again.
QuoteAt this point it is quite possible. The power rail fluctuating can also cause it (the zener should remove most of it).
What you mean? All I'm thinking is the reverse diode in the power supply section which I haven't put there yet.. Something to do with it also? Or the zener does the job?
Quote
Ok an electrolytic probably isn't the right thing for the job there. It could be causing the problem.
Ok. It's what I had unfortunately..
QuoteWhen that circuit came out large bipolars weren't so popular so the designers chose to make their own.
It's probably worth your while changing the cap from a single electrolytic to a non-polar, or doing the two cap thing if you don't have the bipolar caps on hand.
Ok. I'll try to make the testing on the oscilloscope with a non-polar cap (or two equal in reverse series).
Also, could I make a non-polar one by reverse paralleling two of them? It seems right to me also..
I'm seeing now that when I'm messing with "my" depth pot, it is also messing with the LFO frequency! What can I do about that? Someone please?
QuoteWhat you mean? All I'm thinking is the reverse diode in the power supply section which I haven't put there yet.. Something to do with it also? Or the zener does the job?
You would expect the zener to do the job. However if something is wrong, then problems can still show up. What are you powering the pedal from? Look at the power rails with the oscilloscope.
QuoteAlso, could I make a non-polar one by reverse paralleling two of them? It seems right to me also..
Electrolytic caps can conduct when reverse biased so when you put them in "reverse parallel" they will conduct in both directions. So "reverse parallel" is never good. In simple terms think of a electrolytic cap having a diode connected in parallel with the cap. In the correct polarity the diode has no effect but the in reverse polarity the diode conducts and it no longer behaves like a cap. Electrolytics have a complicated internal structure, not just two simple plates, a reverse voltage cause the insulating oxide layer to be removed and it starts to conduct.
QuoteI'm seeing now that when I'm messing with "my" depth pot, it is also messing with the LFO frequency! What can I do about that? Someone please?
Can you post a schematic?
The depth affecting the LFO and the square-wave feed-through might be related.
QuoteYou would expect the zener to do the job. However if something is wrong, then problems can still show up. What are you powering the pedal from? Look at the power rails with the oscilloscope.
Power supply of 9V (not battery yet).
QuoteElectrolytic caps can conduct when reverse biased so when you put them in "reverse parallel" they will conduct in both directions... a reverse voltage cause the insulating oxide layer to be removed and it starts to conduct.
Hmm alright!
QuoteCan you post a schematic?
The depth affecting the LFO and the square-wave feed-through might be related.
(https://i.postimg.cc/TyMbycD0/circ-LFO-ultimo.jpg) (https://postimg.cc/TyMbycD0)
Here 'Tis. I already understood that the depth pot cannot be placed there because it affects the duty cycle, which in connection with the integration time will not give me what I want..
However, I've been searching on the net, and I find that it's possible to do what I want, which is
amplifying the triangle (or attenuating it), and being able to change the
DC offset of it(for the gates of the jFET's, which need to have a certain voltage).
This site mentions one way to do it:
https://electronics.stackexchange.com/questions/162886/non-inverting-op-amp-with-dc-offset
Does it make any sense?
QuoteHere 'Tis. I already understood that the depth pot cannot be placed there because it affects the duty cycle, which in connection with the integration time will not give me what I want..
More the problem is the depth affect the frequency. When you reduce the cap reaches the Schmitt-trigger level earlier and the frequency goes up.
QuoteHowever, I've been searching on the net, and I find that it's possible to do what I want, which is amplifying the triangle (or attenuating it), and being able to change the DC offset of it(for the gates of the jFET's, which need to have a certain voltage).
This site mentions one way to do it:
https://electronics.stackexchange.com/questions/162886/non-inverting-op-amp-with-dc-offset
Does it make any sense?
It's adding an extra stage you don't need. The AC coupled one is going cause unnecessary problems since you lose all you DC levels (not to mention the use of 100R resistors couldn't be worse from a design perspective!)
The depth on these is far more economical,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
https://www.hobby-hour.com/electronics/s/schematics/boss-ce2-chorus-schematic.png
QuoteMore the problem is the depth affect the frequency. When you reduce the cap reaches the Schmitt-trigger level earlier and the frequency goes up.
Exactly.. Not what I wanted. I'd like to have a fixed frequency and then change the amplitude of the wave (but maintain the DC offset)
QuoteIt's adding an extra stage you don't need. The AC coupled one is going cause unnecessary problems since you lose all you DC levels (not to mention the use of 100R resistors couldn't be worse from a design perspective!)
The depth on these is far more economical,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
https://www.hobby-hour.com/electronics/s/schematics/boss-ce2-chorus-schematic.png
Ok.. It's just that I've been searching about shifting the DC levels but cannot find something that's too different than this:
(https://i.postimg.cc/23Q3rWGn/aaaaaaaaaaaaaaaaaa.png) (https://postimg.cc/23Q3rWGn)
Could there be any better way?
As for the circuits you recommended, I'm kind of a dummy to understand these big ones. But I'll try:
For the Boss BF2, the depth is simply a divider of the R48?? I mean, I don't understand what Q8 does there..
For the CE2, the depth is a divider with the R35? And it seems like it''s feeding back to the LFO (maybe the BF2 does too).
I don't seem to understand easily those depth pot's.. If it's just a divider, I've tried to do it but what it does is it actually shifts my DC level also, which is something I didn't want.
Well, thanks to your help with those schematics, I've desiigned a voltage divider with reference to the virtual ground to change amplitude and a voltage divider with reerence to ground to change the DC Offset!
And it works! Do you think it's a good idea?
EDIT: it doesn't, because the voltage divider with reference to ground changes the amplitude of the wave... Does anybody know how to change the DC offset?
Hi everyone.
I'm happy to say that I managed to do a LFO as I wanted.
The circuit is the following:
(https://i.postimg.cc/BLbhQfLR/LFO-7-10-2020.png) (https://postimg.cc/BLbhQfLR)
A quick explanation: down below is the "whole" power supply part, and up is the voltage supply from battery/power supply, which is +9V/0V.
In the middle is the whole LFO.
To the output of U8 where it says "Vastable" is the output of the astable multivibrator. After that there's a voltage divider to set the maximum voltage range preferred by me (the output is by the name of VFullRange). Then there is the potentiometer of depth which changes the voltage range from the maximum value to a minimum value.
And at the end, there's the part where I change the DC Offset to center the triangle where I want, namely the 3.8V (which by the divider made by R12 and R13 - a trimmer - should be 105.5kohm on the R13).
It all looks good and I think I managed to isolate the input of the last op-amp with the previous DC values.
Now the only thing which bugs me is this response:
(https://i.postimg.cc/PNgkc20d/resp-LFO-7-10-2020.png) (https://postimg.cc/PNgkc20d)
(https://i.postimg.cc/nsh8759G/resp2-LFO-7-10-2020.png) (https://postimg.cc/nsh8759G)
Things were doing alright, and this "delay" started after I started messing with capacitor values. Now it's nearly 100 seconds for it to get stable at 3.8V center...
I'm gessing (and hoping) that this is because of the limitations of the capacitor times that Spice takes into account.. And I'm praying that this doesn't happen in real life.. Because everything else is well.
Does anybody know this?
Thanks in advance!
QuoteFor the Boss BF2, the depth is simply a divider of the R48?? I mean, I don't understand what Q8 does there..
For the CE2, the depth is a divider with the R35? And it seems like it''s feeding back to the LFO (maybe the BF2 does too).
I don't seem to understand easily those depth pot's.. If it's just a divider, I've tried to do it but what it does is it actually shifts my DC level also, which is something I didn't want.
You don't need to worry about R48 and R35 they belong to the next part of the circuit If your circuit has such a resistor then leave it it.. The LFO + depth stops at the depth pot wiper.
The difference between the BF2 and the CE2 is the circuit around Q8. The Q8 circuit set the DC level when the Depth pot is minimum. The Manual control lets you set that DC offset. The main thing to realize when the Depth is set at minimum you want want to think about what DC voltage you want. Different DC voltages will also change how the pedal sounds when the Depth pot at other setting, for example mid-way.
QuoteAnd at the end, there's the part where I change the DC Offset to center the triangle where I want, namely the 3.8V (which by the divider made by R12 and R13 - a trimmer - should be 105.5kohm on the R13).
It all looks good and I think I managed to isolate the input of the last op-amp with the previous DC values.
Now the only thing which bugs me is this response:
The circuit is AC coupled. You don't *have to* AC couple the circuit. To AC couple the time-constant of the AC coupling network needs to be long in order to not filter the LFO. The side effect of that is a very long start-up transient. The best way to stop that is to DC couple.
QuoteYou don't need to worry about R48 and R35 they belong to the next part of the circuit If your circuit has such a resistor then leave it it.. The LFO + depth stops at the depth pot wiper.
Yes! My circuit has that of the depth with only a pot really..
QuoteThe difference between the BF2 and the CE2 is the circuit around Q8. The Q8 circuit set the DC level when the Depth pot is minimum.
Why would I want a DC level when the depth pot is at minimum?
Quote
The Manual control lets you set that DC offset.
How? That actually interests me, cause that's what im kinda searching..
QuoteThe main thing to realize when the Depth is set at minimum you want want to think about what DC voltage you want.
Ok. But that's because in that schematic, the LFO changes its center voltage?
Quote
Different DC voltages will also change how the pedal sounds when the Depth pot at other setting, for example mid-way.
For sure, cause the upper side of the LFO wave will be even upper or the lower side even lower.
Quote
The circuit is AC coupled. You don't *have to* AC couple the circuit. To AC couple the time-constant of the AC coupling network needs to be long in order to not filter the LFO. The side effect of that is a very long start-up transient. The best way to stop that is to DC couple.
Ok, this is where I get confused.. All I want is to set the DC level (which was around 4.8V) to center the triangle at 3.8 V.. How can I do it? Or I change the time constant in the circuit I done, or I do a DC couple? Is that it?
I'm just asking about those things because in the morning (which is 10 hours from now ) I'll be able to test it in oscilloscope, etc.
(https://i.postimg.cc/mcBCBv6R/LFO-7-10-2020-2.png) (https://postimg.cc/mcBCBv6R)
Instead of that mambo jambo, I've managed to have a DC offset with a capacitor of a big value, and a resistor connected in one side to the capacitor and other side to the new "DC offset" wanted.
I guess I'm done with the LFO circuit..
Anything that I must keep an eye on?
QuoteWhy would I want a DC level when the depth pot is at minimum?
When the Depth pot is on minimum the circuit has to do *something*. The notches will be fixed so you want to put them in a place that makes the Depth control sound the best of its range of adjustment.
The BF2 has the Manual pot to put that decision in the hands of the user. (Partly because the range of delays is so wide on a flanger).
QuoteOk, this is where I get confused.. All I want is to set the DC level (which was around 4.8V) to center the triangle at 3.8 V.. How can I do it? Or I change the time constant in the circuit I done, or I do a DC couple? Is that it?
When you AC couple it will always have a time constant. You just have to live with it. If you want to get rid of it then DC coupling is the way to go.
Quote
Instead of that mambo jambo, I've managed to have a DC offset with a capacitor of a big value, and a resistor connected in one side to the capacitor and other side to the new "DC offset" wanted.
I guess I'm done with the LFO circuit..
That should work fine. The JFET gates are high impedance so you don't gain anything by adding the buffer.
Quote
Anything that I must keep an eye on?
Only, something to think about.
The way you have the depth varies how widely the sweep is in terms of how far the notches move in frequency. Another type of depth is to reduce the level from the output of the all-pass filter bank. What that does is change the depth of the notches and leaves the sweep "width" the same. The two methods sound different.
QuoteWhen the Depth pot is on minimum the circuit has to do *something*. The notches will be fixed so you want to put them in a place that makes the Depth control sound the best of its range of adjustment.
The BF2 has the Manual pot to put that decision in the hands of the user. (Partly because the range of delays is so wide on a flanger).
Okay I think I understand. In my case when my pot is on minimum, the triangle will almost be DC, so yeah there will be a notch but ordinary people (or even trained) will not listen to it. So it makes sense. How they do it is another story (which maybe I would like to learn in a near future, maybe not now).
Quote
That should work fine. The JFET gates are high impedance so you don't gain anything by adding the buffer.
Of course.. It's just I'm kinda trying to go fast on this and the way that I found to do a DC offset was that one, but I ended up stuck there for hours and found the way that is now in my circuit, after searching lots of places on the web.
Quote
Only, something to think about.
The way you have the depth varies how widely the sweep is in terms of how far the notches move in frequency. Another type of depth is to reduce the level from the output of the all-pass filter bank. What that does is change the depth of the notches and leaves the sweep "width" the same. The two methods sound different.
That is very true and it's something I've been thinking. Anyway I will try do to both on my pedal. Btw, the boss schematics use what depth ? the depth of the notches?
QuoteThat is very true and it's something I've been thinking. Anyway I will try do to both on my pedal. Btw, the boss schematics use what depth ? the depth of the notches?
On a flanger (or chorus or delay) the Depth as you have it might be called Width, Range, and Depth. The alternate form of adjusting depth of the notches is often called "level" or "mix" (possibly depth on some units) because it adjusts the level of the delayed signal.
Quote
On a flanger (or chorus or delay) the Depth as you have it might be called Width, Range, and Depth. The alternate form of adjusting depth of the notches is often called "level" or "mix" (possibly depth on some units) because it adjusts the level of the delayed signal.
Right. Yeah it makes sense to call it mix. I'll try it too.
So with the last LFO circuit that I put above, I'm having problems in the tests...
And by curiosity I went to do a simulation to see how it behaves in 100 seconds:
(https://i.postimg.cc/G8bkLbMm/circ-LFO-test.png) (https://postimg.cc/G8bkLbMm)
What is happening? I thought it would behave good with that 100uF cap..
Well it's the end of my tests and I have some points to ask.
First, let me say I've tested this circuit:
(https://i.postimg.cc/PLCsCGr6/circ-LFO-teste2.png) (https://postimg.cc/PLCsCGr6)
Now I wanted to say 2 things which happened to me:
- the circuit overall was taking like 1 min to stabilize (when I turned it on, it would stay at a higher voltage, and then 60 seconds later the voltage would drop a bit to the desired point), even though the Voltage difference isn't very big.
I have no idea what is happening but it "agrees" with the simulation that I posted above. Maybe it's what Rob said about the time constant, but I wouldn't know how to take it off :/..
- when I messed with a potentiometer far ahead in the circuit, it was slightly affecting the previous parts of the circuit. I noticed that when messing with the depth while seeing the stage before that on the osciloscope input.
I may have an idea of why this is happening, and I'm guessing it's a voltage divider that happens when certain positions of the trimmers/potentiometers are reached.
IF it's that, the way to go would be isolate one part from the other, namely with an op-amp, right?
Maybe I should be posting this elsewhere/starting a new thread.. Please let me know if that's the case.
Thanks in advance.
QuoteI have no idea what is happening but it "agrees" with the simulation that I posted above. Maybe it's what Rob said about the time constant, but I wouldn't know how to take it off :/..
When you power-up a circuit which has different DC voltages each side of a cap the cap must charge-up through whatever circuit resistances it can until a steady-state is reached.
If you think about JFET matching we aimed for better than 50mV matching. That means that circuit needs to stabilize to within say 50mV/2 = 25mV in order to have no noticeable effect. If you have a cap with 2V difference each side the cap voltage needs to stabilize to within 25mV. A cap charging to 2V will reach 2V-25mV = 1.975V in about 4.4 time constants. Your circuit has R=100k and C=100uF, so time constant = RC = 10 seconds. So we are looking at 4.4 * 10 seconds = 44 seconds to stabilize. About the 1 min you are seeing. All rough numbers as the initial 25mV is only a rough estimate.
When you introduce the AC coupling the start-up timing constant comes with it. So the options are:
- reduce the time constant, ie. smaller coupling cap. You can only go so far here as a small cap will start affecting the LFO waveshape at low speeds.
- charge the cap up quicker on power up. Not so easy to do in practice.
- use DC coupling
Quotewhen I messed with a potentiometer far ahead in the circuit, it was slightly affecting the previous parts of the circuit. I noticed that when messing with the depth while seeing the stage before that on the osciloscope input.
I may have an idea of why this is happening, and I'm guessing it's a voltage divider that happens when certain positions of the trimmers/potentiometers are reached.
IF it's that, the way to go would be isolate one part from the other, namely with an op-amp, right?
It depends on the specific problem. An opamp might solve it but, for example, you might be able to just use a higher value pot.
QuoteMaybe I should be posting this elsewhere/starting a new thread.. Please let me know if that's the case.
Up to you.
Quote from: Rob Strand on October 08, 2020, 06:23:09 PM
When you power-up a circuit which has different DC voltages each side of a cap the cap must charge-up through whatever circuit resistances it can until a steady-state is reached...
... use DC coupling
Hmm ok! My cap has aproximately a 1V difference as far as I am aware (4.83 Volt to 3.75 V) but maybe i'm wrong.
You're totally right about the cap values and lower speeds. I actually simulated with way lower caps and with a LFO frequency of 0.3 Hz, the wave would be distorted, and it makes sense actually (the high pass was higher than 1.59 Hz).
In the end I came to the conclusion that a 10uF cap plus a 100k resistance was enough, and it was giving me minus than 5 seconds of stabilization. Very good for me.
(how do I do DC coupling? Just for interest).
Quote
It depends on the specific problem. An opamp might solve it but, for example, you might be able to just use a higher value pot.
Unfortunately I only have 500k pots and 1M pots, but I'm starting to think that 18k/100k divider is the problem..
Anyway to solve the problem with op amps, should I use them as buffers?
I have one punctual question:
(https://i.postimg.cc/jWHHwst5/quest-LFO-10-10.png) (https://postimg.cc/jWHHwst5)
Within this LFO circuit, in the far right, there's, in red, the Vgate. The Vgate is the LFO voltage which is going directly to the jFET gates.
I'm thinking that the 100k ground resistor could make a divider with the FET's, or am I wrong? If i'm right, do I have to do anything in order for it not to happen?
Thanks in advance.
Quote from: savethewhales on October 09, 2020, 08:29:33 PM....100k ground resistor could make a divider with the FET's,
"Ground resistor"?
But yes. Everything is a voltage divider. What is the resistance of one/few JFET Gates?
Quote from: PRR on October 10, 2020, 01:04:42 AM
"Ground resistor"?
But yes. Everything is a voltage divider. What is the resistance of one/few JFET Gates?
You're right.. Vbias resistor.
How can I measure that?
I read that the common sense is to assume JFET input impedance of 1Mega ohm.. IF that's the case, I would have to put a fat resistor at the output of the LFO, just like the Phase 90 one, right?
> assume JFET input impedance of 1Mega ohm..
That would suck. Easily 100Megs. Almost never something to worry about.
https://en.wikipedia.org/wiki/JFET
Quote from: PRR on October 10, 2020, 08:23:35 PM
> assume JFET input impedance of 1Mega ohm..
That would suck. Easily 100Megs. Almost never something to worry about.
https://en.wikipedia.org/wiki/JFET
Alright thanks PRR!!
Hello again guys
I am already testing on a pcb, and for this LFO circuit:
(https://i.postimg.cc/BjgRrGWs/LFO-21-10.png) (https://postimg.cc/BjgRrGWs)
When I turn the depth pot, it is shifting my DC also, which is something I didn't want and didn't design.. What could be causing this? I thought the buffer op-amps would solve this kind of problem but in the way this circuit is, it's not solving..
By the way, the only thing which I wanted to shift my DC is the "Vbias", which is at the end of my LFO circuit and comes from this part of the circuit:
(https://i.postimg.cc/YG16PMVz/LFO-21-10-2.png) (https://postimg.cc/YG16PMVz)
Any kind of help would be very appreciated, and thanks in advance!
Another thing,
As I was going to do tests to my circuit, I was naive because I didn't realize that I had to know what the output wave should look like. I just came to college and started connecting cables.
Now I have a transient response, seen on the oscilloscope, but I don't actually know what should I be seeing coming out of a Phasing circuit, (hope I'm being clear here). When I did transient simulations, with the LFO, I got this in the output of my pedal:
(https://i.postimg.cc/WhLNjr3n/phaser-21-10-3.png) (https://postimg.cc/WhLNjr3n)
Is this what I should be expecting? (No I haven't got this in the output yet, on my oscilloscope)
Well I guess I did it now. This is what I got on the oscilloscope:
(blue wave - with feedback on)
(https://i.postimg.cc/dDDJcFYJ/TEK0011.png) (https://postimg.cc/dDDJcFYJ)
(blue wave - feedback off - different frequency than the above)
(https://i.postimg.cc/bsfRbzLT/TEK0000-9.png) (https://postimg.cc/bsfRbzLT)
Well, I managed to solve the last two problems of the last two posts I did (should I delete them?)
The thing is: The circuit worked perfectly (after, of course having mistakes like soldering wrongly a potentiometer, and other problems which were solved later.)
These are images of what I was seeing on the oscilloscope (Phaser circuit - input yellow vs output blue):
(if I'm not mistaken)
Everything on max (range of the LFO, ressonance, mix/ammount and speed of the LFO):
(https://i.postimg.cc/w1XCn0fk/TEK0007-3.png) (https://postimg.cc/w1XCn0fk)
Maybe everything on minimum:
(https://i.postimg.cc/2LLJGwLh/TEK0005-4.png) (https://postimg.cc/2LLJGwLh)
I don't kknow exactly the settings:
(https://i.postimg.cc/McRm9F9W/TEK0011.png) (https://postimg.cc/McRm9F9W)
More zoom (yes bad connections):
(https://i.postimg.cc/8JSB9mYL/TEK0010-2.png) (https://postimg.cc/8JSB9mYL)
LFO behaviour:
(https://i.postimg.cc/5YbLnNH3/TEK0006-4.png) (https://postimg.cc/5YbLnNH3)
(https://i.postimg.cc/K4s3g55Q/TEK0001-7.png) (https://postimg.cc/K4s3g55Q)
With the speed on maximum it behaves like this (which I don't care too much because it isn't even noticeable auditively, I suppose - it's 9 Hz of frequency):
(https://i.postimg.cc/06fb5GQY/TEK0002-6.png) (https://postimg.cc/06fb5GQY)
All of this is just to say that the circuit works, everything seems fine for now. Next step is getting a "box" for it and delivering the right power, with true bypass, battery and 9V power switch, LED, which I will do when I have my hands on the "box". I already know how I will do the connections, and hopefully everything will go right.
So thank you soooo much to all of you who responded me here during the time I was here making questions.
Without you this would be absolutely nothing.
I'm writing the project now and I wanted to explain some things I've done with the pedal circuit, however, there's this part of the circuit, which is the LFO:
(https://i.postimg.cc/k2CST6xR/circ-final-phaser-LFO.png) (https://postimg.cc/k2CST6xR)
And the LFO is based on a non inverting Schmitt Trigger followed by an integrator, but I don't know how to explain the values I got.. All I did was to basically learn the basic which was that the two positive feedback resistances established Upper and lower thresholds and I went on to experiment to get a good result by seeing the triangle on the oscilloscope. I don't seem to be able to get there by doing reverse calculations..
These are the sims taken directly from the circuit shown:
(https://i.postimg.cc/ppHyvNyg/LFO-response-26-10.png) (https://postimg.cc/ppHyvNyg)
Where the square is the output of the schmitt trigger and the Vastable is the output of the integrator (triangle).
By searching on the web I came to discover that the equations for the Upper and Lower thresholds of the Schmitt -Trigger are
- VUT(voltage upper threshold)=(1+47k/270k)Vref+Vcc*47k/270k
- VLT(Voltage lower threshold)=(1+47k/270k)Vref+(-Vcc)*47k/270k
But when I go and calculate it, the values don't actually go right with the simulations I did on Spice... Can somebody help me please? Thank you very much in advance.
I don't know why it is not cooperating, but...
What do U11 U12 do ?
If R38 e R39 is made a 10k pot, why does it need U10?
C11 and C12 different values opposite directions?
R32??
It does not have to be this complicated.
I'm assuming you are only interested in the oscillator around U7 and U8.
Also the sims are the signals at those IC's. Yes?
So I started with these equations
(Vref - VLO) /47k =( VOH -Vref)/270k
(VHI - Vref) /47k =(Vref -VOL)/270k
Which simplify to,
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref - VOL * 47k/270k
The Schmitt input thresholds are VLO and VHI.
The opamp VOH and VOL are the output levels at the point marked SQUARE, the output of U7.
Your equations use +/-Vcc but in reality VOH is about +Vcc-1.5 and VOL is -Vcc + 1.5V, as the opamp doesn't swing fully to the rails.
So here's where I get confused. On your sim U7 is powered from +/- Vcc so you would expect U7 to swing +/-Vcc (or the more accurate levels I just quoted). However your U7 is swinging 1.5V to 7.5V. It looks like U7 is powered from 0V and Vcc.
So that's definitely a source of a problem. I can't see why on your sim. Maybe probe the DC voltages on the power pins of U7 or check the connections on the schematic. See if you can work out why U7 isn't swing to the correct voltage.
Also I couldn't see what voltage you used for Vref on the schematic.
QuoteSo that's definitely a source of a problem. I can't see why on your sim. Maybe probe the DC voltages on the power pins of U7 or check the connections on the schematic. See if you can work out why U7 isn't swing to the correct voltage.
Do you actually have a -Vcc power source? maybe U7 is running from nothing on the negative rail?
Quote
What do U11 U12 do ?
If R38 e R39 is made a 10k pot, why does it need U10?
C11 and C12 different values opposite directions?
R32??
It does not have to be this complicated.
U11 and U12 separate the astable output from the Vfullrange part and the Vfullrange from the depth, respectively. Actually I've done this because when I changed one of the parts, the output would behave as if I was chaning the other one too, which was something I didn't want. Same thing with U12 (separating).
C11 and C12 serve as a solution for me not having a 10uF polarised capacitor. When in reverse series, the equivalent value is 1/(1/C11+1/C12). In this case I get a 9.09 uF polarised capacitor.
R31=Pad for the speed of the triangle, without it I was getting too fast of an LFO and R32 is a 470k pot that defines the speed of the triangular wave.
Quote from: Rob Strand on October 26, 2020, 05:33:28 AM
I'm assuming you are only interested in the oscillator around U7 and U8.
Yes!
Quote
Also the sims are the signals at those IC's. Yes?
Yes!
Quote
So I started with these equations...
...The opamp VOH and VOL are the output levels at the point marked SQUARE, the output of U7.
ok!
Quote
Your equations use +/-Vcc but in reality VOH is about +Vcc-1.5 and VOL is -Vcc + 1.5V, as the opamp doesn't swing fully to the rails.
So here's where I get confused. On your sim U7 is powered from +/- Vcc so you would expect U7 to swing +/-Vcc (or the more accurate levels I just quoted). However your U7 is swinging 1.5V to 7.5V. It looks like U7 is powered from 0V and Vcc.
It is right then everything you said. Power is +9V to 0V, sorry for not bringing this here before.
Quote
Also I couldn't see what voltage you used for Vref on the schematic.
Vref is 4.8 Volt exactly (coming from the 5.1V Zener)
QuoteDo you actually have a -Vcc power source? maybe U7 is running from nothing on the negative rail?
This is how my circuit is operating (I know it's strange but helps me understanding the working of the LFO itself)
(https://i.postimg.cc/56xX01Kd/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa.png) (https://postimg.cc/56xX01Kd)
OK, so when I plug in the values I get a good match with your spice sim.
Notice I'm using 1.5V and 7.5V for the opamp swing.
Thresholds:
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref - VOL * 47k/270k
Opamp Swing
VOH 7.5
VOL 1.5
Vref 4.8
Calculated
VLO 4.33
VHI 5.37
Value by eye from spice output
VLO 4.4
VHI 5.35
The calculations and the spice output agree to better than 0.1V
So perhaps the problem was you used -Vcc as -9V instead of 0V?
Quote from: Rob Strand on October 26, 2020, 06:28:57 AM
Thresholds:
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref - VOL * 47k/270k
Opamp Swing
VOH 7.5
VOL 1.5
Vref 4.8
Calculated
VLO 4.33
VHI 5.37
Value by eye from spice output
VLO 4.4
VHI 5.35
The calculations and the spice output agree to better than 0.1V
yesyesyesyes that's indeed right. Thank you so much. I guess I was confusing the equations (but not confusing -vcc actually)
Is it right to assume that the inverting and non-inverting pins in the schmitt-trigger have the same voltage Vref?
Actually I already understood that yes, they do, because I did the math to get to the equation Rob posted here, but I wanted to know if there's anything else to take into account around this matter.
Thanks
Well I actually am trying to get to Rob's equation by node analysis and I don't seem to be getting it right..
I am considering now the V+ point differently from the Vref point, and the way that I am dealing with the Vin being leftover in the equation is by subtracting the VLT from the VUT but in that way I can't seem to discover what Vin actually means.. Could I substitute it for the value of Vref? No, right?
QuoteIs it right to assume that the inverting and non-inverting pins in the schmitt-trigger have the same voltage Vref?
That's the main idea.
Quote
Actually I already understood that yes, they do, because I did the math to get to the equation Rob posted here, but I wanted to know if there's anything else to take into account around this matter.
For more accurate results you can take into account the fact the opamp output doesn't swing 0V to VCC but swings approximately VOL=0V+1.5V = 1.5V to VOH = VCC-1.5V = 7.5V.
That's a finer point which makes things more confusing. It also makes the equations a little messier.
Quote
Well I actually am trying to get to Rob's equation by node analysis and I don't seem to be getting it right..
I am considering now the V+ point differently from the Vref point, and the way that I am dealing with the Vin being leftover in the equation is by subtracting the VLT from the VUT but in that way I can't seem to discover what Vin actually means.. Could I substitute it for the value of Vref? No, right?
Well I could have made a mistake but I was fairly convinced the equations were OK since it matches the sim.
It can be confusing analysing Schmitt trigger because it has a two states. You are currently in one state and you want to find what input voltage changes the state. There are two states and two such voltages. The change of state occurs when the opamp input voltages are equal.
The best way to start is to "pick" a stable state to start in. So if you think of the input as being low opamp +input will be below -input and the opamp output will be low. The opamp output being low is consistent with opamp +input still being low, so it is stable state.
You want to opamp output to change from the stable low-state to high. To do that the opamp + input must rise towards Vref, then when it hits Vref it will change state. The opamp output is low so that's pulling the opamp +input down, so in order raise the opamp + input to Vref the input signal (VIN) must rise above Vref. When that occurs the input voltage is at the upper Schmitt threshold VHI.
So with positive currents down the resistors the point where the opamp +input is at Vref requires,
(VHI - Vref) /47k =(Vref -VOL)/270k
Next is to do a brain switch. Assume the opamp output is in high stable state and the voltage is VOH. You go through the same type of thinking that the opamp +input must be high and the opamp output is high and you have a stable state. To change the state the input voltage (VIN) need to decrease until the opamp +input drops to Vref. Since the opamp output is high the only way that will happen is when VIN is below Vref. That's the lower Schmitt input threshold VLO.
So now the opamp output is at VOH and current flows from the opamp output down the feedback resistor then down through the input resistor. At the point where the opamp +input is at Vref, assuming all positive currents,
(Vref - VLO) /47k =(VOH -Vref)/270k
The key is to think of the voltages required to be in a stable state then think of the input going up or down and hitting the point which will change the state. The point where the state changes is when the opamp inputs become equal, in your case when the opamp +input hits Vref.
Quote
For more accurate results you can take into account the fact the opamp output doesn't swing 0V to VCC but swings approximately VOL=0V+1.5V = 1.5V to VOH = VCC-1.5V = 7.5V.
Yeeah I'm doing that.
Quote
It can be confusing analysing Schmitt trigger...
...in your case when the opamp +input hits Vref.
Ok sooo what you're saying is the state STARTS changing when +input hits Vref but FINISHES changing when the +input hits VLO?
It may not be what I'm saying, and if it's not, I wonder where do the VHI and VLO come into place here. Because as you mentioned the change starts at the Vref (which doesn't make sense because I have 2 thresholds designed for exactly this not happening.)
The op amp will try to equal the inputs all the time, as far as I am aware, right? If so, how come the non inverting input isn't always Vref?
Quote
(VHI - Vref) /47k =(Vref -VOL)/270k
This is what I didn't get. For me everything seemed clear, except for the fact that for the High threshold, we're doing calculations with the low output of the op amp...
I think I'm getting there, it's just a little bit more of something which I'm not getting.
QuoteThe op amp will try to equal the inputs all the time, as far as I am aware, right? If so, how come the non inverting input isn't always Vref?
No, it's not true. This circuit is non-linear so it doesn't have to follow that rule.
There's two concepts you need to understand:
Opamp Saturation and Positive Feedback (and hysteresis)
Take an opamp without any feedback resistors or input resistors. If we tie the opamp -input to Vref then when the opamp +input greater than Vref the opamp output will swing positive. The opamp has a very large gain A and the opamp output voltage tries to hit,
Vout = A * Vdiff
where,
Vdiff = "V at +input" - "V at -input".
If A is 100000 and power rail is 9V then with Vdiff = 1mV the opamp output tries to get to 100000*1mV = 100V but 100V is greater than the power supply voltage so the output get stuck at 9V. We say the opamp saturates, or clips. So what if we increase the input further to say 2mV, the output is still stuck at 9V. In fact for any Vdiff > +90uV the output is stuck. When we force the input like this the opamp +input does not have to match the opamp -input (=Vref).
When we have negative feedback the feedback resistor keeps Vdiff at 0V. However we can still clip the opamp. When clipping occurs the output will get stuck at 0V or 9V and Vdiff will actually become non-zero. Negative feedback tries to make it zero but the clipped output stops that from occurring.
We can simplify the above for an ideal opamp with infinite gain that when Vdiff > 0 the opamp output saturates positively and gets stuck at the positive supply rail, and when Vdiff < 0 the opamp output saturates negatively and gets stuck at the negative supply rail.
The point here is the
- output stuck in saturation
- the input voltage can change without having an effect on the output.
- only Vdiff > 0 or Vdiff < 0 can change the output
(in you case think of opamp +input > Vref or opamp +input < Vref)
QuoteOk sooo what you're saying is the state STARTS changing when +input hits Vref but FINISHES changing when the +input hits VLO?
...
It may not be what I'm saying, and if it's not, I wonder where do the VHI and VLO come into place here. Because as you mentioned the change starts at the Vref (which doesn't make sense because I have 2 thresholds designed for exactly this not happening.)
I understand where you are getting stuck.
The two thresholds come about because the opamp output voltage can be in two states (high and low). The state moves the threshold.
When the output is stuck at 0V, there is a whole range of voltages where Vdiff < 0 and the output will stay stuck at 0V. For example we can increase the input voltage from 0V to just under the threshold (VHI) and provided Vdiff is < the opamp output will stay at 0V. If Vdiff is just under 0V we can decrease the circuit input voltage again and Vdiff well got more negative and the opamp output doesn't change.
The threshold is the point where we change the output from 0V to 9V. For that to happen Vdiff must increase from Vdiff < 0, hit Vdiff = 0V, then when Vdiff is just above 0V the opamp output will swing to 9V.
Suppose we increase the circuit input so Vdiff just above zero. In your Schmitt trigger the feedback resistor connects back to the opamp +input. When the opamp output rise from 0V to 9V that resistor *increases* the voltage on the opamp +input. So once you hit Vdiff > 0 the opamp drives *itself* harder into saturation. This is called positive feedback. Look what happens not if we back off the circuit input voltage. The *circuit* input is currently at the threshold VHI. If we try to decrease circuit input voltage like we did before the output changed state we can't make Vdiff < 0. The positive feedback as now "lifted" the opamp +input and made Vdiff *even more positive*. So now if we want to make Vdiff < 0 we need to decrease the circuit input to less than the VHI threshold. The new threshold is the VLO threshold. The positive feedback changes the point where Vdiff hits zero depending on the voltage at the output of the opamp.
FWIW, the different threshold for increase and decreasing signals is called Hysteresis. In order to get Hysteresis you need memory
which remembers the state. In the case of a Schmitt-trigger the opamp output is remembering what state it is currently in.
This pic shows how the thresholds change depending on the (output) state.
[click to enlarge]
(https://i.postimg.cc/fVJPgnTS/Basics-of-Schmitt-Trigger-Non-Inverting-Hysteresis.jpg) (https://postimg.cc/fVJPgnTS)
I strongly suggest using spice to look at the opamp +input on your Schmitt trigger. There will be a triangle wave going up and down but there will also be up/down shifts in the opamp +input voltage. The Schmitt trigger changes state when the opamp +input hits Vref. However the change in the opamp output voltage raises and lower the opamp +input so the input needs to reach two different thresholds.
I don't know if this helps at all. It can be a little tricky to understand.
Quote
The point here is the
- output stuck in saturation
- the input voltage can change without having an effect on the output.
- only Vdiff > 0 or Vdiff < 0 can change the output
(in you case think of opamp +input > Vref or opamp +input < Vref)
Ok, got it!
Quote
Suppose we increase the circuit input so Vdiff just above zero...
...The positive feedback changes the point where Vdiff hits zero depending on the voltage at the output of the opamp.
This is like when it reaches Vref, it goes even further positively, to the VUppertreshold? It makes sense.
Quote
I strongly suggest using spice to look at the opamp +input on your Schmitt trigger. There will be a triangle wave going up and down but there will also be up/down shifts in the opamp +input voltage. The Schmitt trigger changes state when the opamp +input hits Vref. However the change in the opamp output voltage raises and lower the opamp +input so the input needs to reach two different thresholds.
Okkk understood. Here go the sims:
(click to enlarge)
(https://i.postimg.cc/jCTYgzdb/LFO-27-10.png) (https://postimg.cc/jCTYgzdb)
So I'll try to draw some conclusion:
The output goes high, it's because the +input hit the Vref threshold. However, because it is on positive feedback, the input voltage (which is different from the +input) gets pushed to above Vref to a rate which depends on the resistor network put there. Is that it?
However I'm not getting why the +input gets pushed to even higher than the triangular wave itself.. wouldn't the triangle wave have that same peak?
Quote
I don't know if this helps at all. It can be a little tricky to understand.
Helps even too much.
One thing is I understood the working of the Schmitt-Trigger circuit, and it's principle, however what I didn't understood was something specific about the final equation that you wrote down.
-> (VHI - Vref) /47k =(Vref -VOL)/270k
Again, we're doing calculations for the VHI (higher treshold), but taking into account the Low output VOL, why?
I thought since the VHI makes the circuit change output to VOH, what should be in the equation shouldn't be VOL but VOH in this case...
QuoteThis is like when it reaches Vref, it goes even further positively, to the VUppertreshold? It makes sense.
Yes. It moves up but not to VUpperthreshold. VUpperthreshold and VLowerthreshold only have meaning for the signal input node. The voltages at +input of the opamp have a different scaling to the signal input. The important thing is the voltage moves up and down, it's not helpful think of amount the voltage changes at the opamp + input. The other important thing is output changes state when the opamp +input reaches Vref.
QuoteHowever I'm not getting why the +input gets pushed to even higher than the triangular wave itself.. wouldn't the triangle wave have that same peak?
Suppose the input signal is at the peak of the triangle and the opamp out is at VOL. The opamp +input reaches Vref, so the opamp output changes state from VOL to VOH. When that happens the opamp +input *must* increase in voltage, because of the feedback resistor. So that means the voltage must be higher than the triangle's peak. Look at you sim, notice how the "shifted" triangles always aim *towards* Vref and the output changes state when it hits Vref. It doesn't matter if the triangle is going up or down the signal on the opamp +input always aims at Vref. The output changes can only occur when the opamp +input hits Vref.
QuoteOne thing is I understood the working of the Schmitt-Trigger circuit, and it's principle, however what I didn't understood was something specific about the final equation that you wrote down.
-> (VHI - Vref) /47k =(Vref -VOL)/270k
Again, we're doing calculations for the VHI (higher treshold), but taking into account the Low output VOL, why?
I thought since the VHI makes the circuit change output to VOH, what should be in the equation shouldn't be VOL but VOH in this case...
(https://i.postimg.cc/L8TM52cD/Basics-of-Schmitt-Trigger-Non-Inverting-Hysteresis.jpg)
Check out this pic. When we hit the upper threshold VUT, just before that the output is at -Vsat (which is VOL). You can see the same effect for VLT, it depends on +Vsat (which is VOH). When you look at the thresholds you need to think about what the opamp output level is upto now, not what it will changes to.
The way to think about is is while the output is at VOL, the feedback resistor is pulled down, the opamp +input is pull down below Vref. So in order to increase the opamp +input to Vref then signal input must be higher threshold VHI (or VUpperthreshold or VUT). Similarly if the opamp output is currently at VOH it's going to raise the opamp +input above Vref so in order to decrease the opamp +input the signal input must be the lower threshold VLO (or VLowerthreshold or VLT).
QuoteIt moves up but not to VUpperthreshold...
... The output changes can only occur when the opamp +input hits Vref.
I guess you made it clear to me.. the noninverting goes up because of the feedback and to be able to return to Vref it needs a little help from the input voltage (which needs to reach VLT).
QuoteWhen we hit the upper threshold VUT, just before that the output is at -Vsat (which is VOL)...
... Similarly if the opamp output is currently at VOH it's going to raise the opamp +input above Vref so in order to decrease the opamp +input the signal input must be the lower threshold VLO (or VLowerthreshold or VLT).
Okk makes sense. I'm doing math for when I'm going to change to VUT and for that I must take into account that right before I change, I'm at -Vsat, right?
And for this situation I just wrote, the equation should be (VUT-Vref)/R14=(Vref-VOL)/R12 I assume?
QuoteOkk makes sense. I'm doing math for when I'm going to change to VUT and for that I must take into account that right before I change, I'm at -Vsat, right?
Correct.
QuoteAnd for this situation I just wrote, the equation should be (VUT-Vref)/R14=(Vref-VOL)/R12 I assume?
Yep, that's it.
Rob, I remember a while back when I was messing with the LFO and it was not working you advised me to use a non-polar capacitor instead of the polar cap I was using on the integrator (and was having bad results). In the end I changed it and it worked, but I don't really know how to explain why (because I think I don't even know). Could you explain that to me? Thanks!
Another thing is: I used two polarised caps in reverse series to substitute a non-polar cap (because I didn't have the value). But again, I don't know how this actually works and I've been searching for any literature/papers/trustworthy sites and I can't seem to find anything that explains to me why that works and why the total capacitance values (at low voltages) are 1/Ceq=1/C1+1/C2. Any help on this matter would be greatly appreciated.
QuoteRob, I remember a while back when I was messing with the LFO and it was not working you advised me to use a non-polar capacitor instead of the polar cap I was using on the integrator (and was having bad results). In the end I changed it and it worked, but I don't really know how to explain why (because I think I don't even know). Could you explain that to me? Thanks!
Another thing is: I used two polarised caps in reverse series to substitute a non-polar cap (because I didn't have the value). But again, I don't know how this actually works and I've been searching for any literature/papers/trustworthy sites and I can't seem to find anything that explains to me why that works and why the total capacitance values (at low voltages) are 1/Ceq=1/C1+1/C2. Any help on this matter would be greatly appreciated.
It not easy to explain. Once you get past 1/Ceq=1/C1+1/C2 the explanation becomes very detailed and you need to know what happens inside the caps.
If you go here and read through articles 5 and 6 they cover some of the points.
https://linearaudio.nl/cyril-batemans-capacitor-sound-articles
Don't feel bad if you quickly feel like it's all to hard ;D. You can just say it is/was a common method of making a bipolar capacitors from electrolytic capacitors.
Quote
It not easy to explain. Once you get past 1/Ceq=1/C1+1/C2 the explanation becomes very detailed and you need to know what happens inside the caps.
If you go here and read through articles 5 and 6 they cover some of the points.
https://linearaudio.nl/cyril-batemans-capacitor-sound-articles
Don't feel bad if you quickly feel like it's all to hard ;D. You can just say it is/was common method of making a bipolar capacitors from electrolytic capacitors.
Ok, I've read some things, including the articles you put and I think i have an idea of how it works, I'll be writing what I know by now in my job.
Also, I read in the article 6 that the bipolar caps are done with two polar caps but in place of the
unformed cathode foil they use a second, formed, anode foil.
I actually quoted Cornel Dubilier in my job, which is the founder of CDE (they make capacitors for a big while now).
Anyway I'm not toooo worried but I would like to be able to explain at least a little bit of what's going on (if I'm asked to in my presentation).
Thanks
Quote from: savethewhales on October 27, 2020, 09:25:31 PMI actually quoted Cornel Dubilier in my job, .... Anyway I'm not toooo worried but I would like to be able to explain at least a little bit of what's going on (if I'm asked to in my presentation).
You might want to count and note the number of "L"s in Cornell, for formal work.
Dubilier was quite a guy. I have not found where Cornell comes in.
https://en.wikipedia.org/wiki/William_Dubilier
https://en.wikipedia.org/wiki/Dubilier_Condenser_Company
(https://i.postimg.cc/K373mKJ1/Dubilier-age22-42.jpg) (https://postimg.cc/K373mKJ1)
QuoteI have not found where Cornell comes in.
It comes from "Cornell Radio". It may have to do with Dubilier coming from New York.
Perhaps "Cornell Radio" was a New York company.
You guys from the US would be able to guess the links better than me.
> It comes from "Cornell Radio".
That's what the current owners say. They weren't there. The likely partner is Cornell Electric Manufacturing Corp. (https://www.radiomuseum.org/dsp_hersteller_detail.cfm?company_id=14644), New York, Manufacturer of voltage supplies (battery eliminators). Not a major technology but maybe knew the right people in the right stores.
QuoteThat's what the current owners say. They weren't there. The likely partner is Cornell Electric Manufacturing Corp., New York, Manufacturer of voltage supplies (battery eliminators). Not a major technology but maybe knew the right people in the right stores.
It's hard to know what the truth is. I couldn't find any announcements for the name change or mergers.
It seem the Dubilier name remained in the UK after 1933, and didn't change until 1935 to 1938.
I did find this odd document,
https://ethw.org/w/images/9/90/Dubilier_-_Radio_Catalogue_and_Dealers_Guide%2C_1925-1926.pdf
"Dubilier Condensor" and "Radio Corporation" (NY)
Presumably Radio Corporation is RCA before they split from GE.
From 1928 to 1933 there was apparently a court case between RCA and Dubilier so I can't imaging they would merge. Yet it is odd it's about the same period.
After that history skips forward to 1938-1939 with a new name.
The front section shows promise but then says nothing!
https://ethw.org/w/images/5/55/Dubilier_-_Catalog_No._161,_1938-39.pdf
> Presumably Radio Corporation is RCA before they split from GE.
No way. RCA was eat-only: nobody survived after RCA (until Sarnoff left this world).
Everybody was a "radio corporation".
Dubilier was mica-caps, then added electrolytics and other types. The Cornell I linked was selling battery eliminators, meaning they bought lots of caps. Or made them. But certainly sold lots of cap-filled products. I could see them joining forces to dominate the cap market. Or one or the other falling behind on his rent and a forced merger. Those catalogs you link are from William's own library, but marked Florida. Several businessmen who visited FLA in that period just didn't come back north again. Dubilier may have sold to Cornell and retired to Florida.
QuoteEverybody was a "radio corporation".
Yes, that's the way to read it.
QuoteDubilier was mica-caps, then added electrolytics and other types. The Cornell I linked was selling battery eliminators, meaning they bought lots of caps. Or made them. But certainly sold lots of cap-filled products. I could see them joining forces to dominate the cap market. Or one or the other falling behind on his rent and a forced merger. Those catalogs you link are from William's own library, but marked Florida. Several businessmen who visited FLA in that period just didn't come back north again. Dubilier may have sold to Cornell and retired to Florida.
I didn't think about checking he might have got out of the company, or even checking when.
I did find something stuff narrowing the name change down to late 1933 to early 1934. I guess that agrees with the 1933 merger claim.
Dubilier
Filed Jan 1933,
https://patentimages.storage.googleapis.com/aa/e9/a5/e4b6ee339113cb/US2130532.pdf
Filed April 1933
https://patentimages.storage.googleapis.com/39/61/8e/935dbe8a5a3696/US1970776.pdf
Filed Aug 1933
https://patentimages.storage.googleapis.com/d8/75/b8/ecc51bc5278979/US2070435.pdf
Cornell-Dubilier
Filed Aug 1934
https://patentimages.storage.googleapis.com/58/2d/ca/7c69983bee960d/US2088693.pdf
https://www.cde.com/resources/catalogs/AEappGUIDE.pdf
This is what I quoted from. It's under the name of Cornell Dubillier Electronics (or smth like that). It has few information about who actually wrote it and specific things like dates.
What I know is that seems well written and has valuable information.
https://linearaudio.nl/sites/linearaudio.net/files/Bateman EW 01 2003 mar2003 10 to 100uF caps and 100 Hz measurements_0.pdf
This is the Bateman, C. document I quoted.
Either way I don't know too much of history around caps but I was told that CDE was a know manufacturer of caps..
QuoteThis is the Bateman, C. document I quoted.
Either way I don't know too much of history around caps but I was told that CDE was a know manufacturer of caps..
That info is all fine.
Quote from: Rob Strand on October 29, 2020, 02:04:23 AMhttps://patentimages.storage.googleapis.com/58/2d/ca/7c69983bee960d/US2088693.pdf
Yum, nitrobenzol! Better than Halowax! Now called Nitrobenzene (https://en.wikipedia.org/wiki/Nitrobenzene), and produced in the millions of tons, Nitrobenzene is a notorious poison.
QuoteYum, nitrobenzol! Better than Halowax! Now called Nitrobenzene, and produced in the millions of tons, Nitrobenzene is a notorious poison.
The last 100 years has been quite frightening chemical wise. Old capacitors had all sorts of evil stuff in them. Even upto the 70's we were pretty stupid. There's still a lot of cracks. The large hardware outlets still sell non-animal friendly snail bait There's even deceptively marked animal friendly versions which say poisonous if eaten by pets. Plenty of poisonous chemical in paints for dumb consumers to wash down their kitchen sinks. You can't trust people with anything evil in the MDS, they have no idea what it means.
Found this one, Sept 1933, adverts for Cornell-Dubilier,
https://worldradiohistory.com/Archive-Service-Magazine/30s/Service-1933-09.pdf
So I guess that narrows the name change to Aug/Sept 1933.
Previous ad in the same mag was in, Feb 1933, under Dubilier Condensors,
https://worldradiohistory.com/Archive-Service-Magazine/30s/Service-1933-02.pdf
For the name I got a similar name to what you found previously,
"In 1933, Dubilier's company merged with the Cornell Electric Company to form the Cornell-Dubilier Electric Corp."
https://www.electronicdesign.com/technologies/components/article/21795312/william-dubilier
And
http://ai.eecs.umich.edu/people/conway/Awards/ElectronicDesign/ED%20Hall%20of%20Fame%202002.pdf
Hey!! Do you guys know what's the normal output voltage of a guitar signal? I've read so many different things: -10 dBV, -20 dBV, 100 mV RMS, 3V RMS.. I can't really understand what would be correct..
I'm just asking this because tomorrow I'll have to do tests on my pedal but I need them to be at a reasonable level for guitar outputs.
Thank you very much for your attention and help,
Cheers
Hey guys!!
I really need some help, I've already done some tests on my pedal on an Audio Analyser (APX), and I was having this response (with the circuit INSIDE the pedal box):
(https://i.imgur.com/ULpzxjYh.png?1)
Different trimmer position:
(https://i.imgur.com/ijZzyd0h.png?1)
BUT Now after some time without testing it (because I had to go to work these days), I went to test it again and this is what I was having:
(https://i.imgur.com/iP0gNae.png?1)
(https://i.imgur.com/zxhCTv5.png?1)
Does somebody know what might be going on here?
There's some things I did:
- Tested continuity in all of the circuit (except the LFO, which I seen on the oscilloscope and was behaving ok) and everything seemed to be connected (but of course there's some problem here).
- Changed cables (this helped me to avoid the -5 dB ceiling, otherwise getting 0)
- Seeing the frequency response at the op amp outputs. The 1st op amp of the phase shifting stage was alright, the 2nd was alright, but the 3rd was like this:
(https://i.imgur.com/pcjsGw7.png?1) (when I continued, the slope was the same).
Knowing that the response should supposedly be of 0 gain throughout the whole spectrum (because in the ouput of the 2nd op amp of the phase shifting stage it was like this), I concluded it was happening a problem of high pass filter somewhere around the 3rd op amp (I don't even know where exactly could this be happening...)
So I started checking frequency response on the terminals of components near that area.
For the sakes of me trying to explain myself and you guys understanding what the hell am I saying, I put down here the schematic on LTSpice and schematic on EasyEda (which is the definitive final one, in terms of values).
LTSpice (imgur link to see better https://imgur.com/X0W84Dg):
(https://i.imgur.com/X0W84Dgh.png?1)
EasyEda (I know it's a mess.. if you guys want I can try to make it to 2 different images for better visualization):
(https://i.imgur.com/ULae6yYh.png?1)
Talking EasyEda, I got (Note that I refer to "bad" as the high pass unwanted freq response):
- Left leg of R18: good
- Right leg of R18: bad
- Before R15: good
- Between R15 and R14: bad
- Out1 of U5 (TL072): good
- Pin 6 of U5: bad
- Pin 5 of U5: bad
- Pin 1 of Q3: bad
- R13 on the upperside: bad
- Right leg of cap U7: bad
- Left leg of cap U7:
(https://i.imgur.com/U90UyMD.png?1)
- Both sides of R14: bad
- One of the legs of cap U9: bad;
Other leg of U9:
I got these 2 little different responses from 2 different testings:
(https://i.imgur.com/N6naUyx.png?1)
(https://i.imgur.com/6fYdbXnh.png?1)
These were the ones I could take note of, but I will be testing the rest of the points on college on monday.
I'd really appreciate any kind of help that you guys could give me.. I am actually lost.
We have to wait for the image service to come back on-line.
Some conversations are going to get difficult without images.
Plenty of places you can have your images hosted - imgur.com (http://imgur.com) for one.
Quote from: bluebunny on November 15, 2020, 06:28:39 AM
Plenty of places you can have your images hosted - imgur.com (http://imgur.com) for one.
Thank you soo much! I just updated the post I had done, with images from imgur. Hope you guys can see it good.
When you upload your picture to imgur, hover over your picture and click on the "..." on the top right, then click on "Get share links". Now click on "Copy Link" next to the "BBCode (Forums)" option:
(https://i.imgur.com/cfE2jd3.png)
You can paste this directly into your post, where your picture become visible in-line. Then we don't have to go chasing your links. (And it's exactly what I did to show the picture you see above these words.)
Quote from: bluebunny on November 15, 2020, 12:34:08 PM
When you upload your picture to imgur, hover over your picture and click on the "..." on the top right, then click on "Get share links". Now click on "Copy Link" next to the "BBCode (Forums)" option:
(https://i.imgur.com/cfE2jd3.png)
You can paste this directly into your post, where your picture become visible in-line. Then we don't have to go chasing your links. (And it's exactly what I did to show the picture you see above these words.)
Thank you very much! unfortunately, some images are too big now.
UPDATE: Now everything is ok at the post!!!
Quote from: savethewhales on November 15, 2020, 12:48:03 PM
some images are too big now.
Apart from resizing your pictures before you upload them, you can also make them
appear smaller by including
HEIGHT=nnn (or
WIDTH=nnn) inside the
[IMG] tag. Like this:
(http://www.bouron.org.uk/marc/bluebunny.jpg)
[img height=20]Or this:
(http://www.bouron.org.uk/marc/bluebunny.jpg)
[img height=120]And the reader can click on the image to see it full-size if they wish.
Quote from: bluebunny on November 15, 2020, 04:20:44 PM
Quote from: savethewhales on November 15, 2020, 12:48:03 PM
some images are too big now.
Apart from resizing your pictures before you upload them, you can also make them appear smaller by including HEIGHT=nnn (or WIDTH=nnn) inside the [IMG] tag. Like this:
(http://www.bouron.org.uk/marc/bluebunny.jpg) [img height=20]
Or this:
(http://www.bouron.org.uk/marc/bluebunny.jpg) [img height=120]
And the reader can click on the image to see it full-size if they wish.
Thanks! But I guess i'll let these ones stay like this, and if someone asks me for resizing or smth, maybe i'll do it!
Quote from: savethewhales on November 15, 2020, 12:48:03 PM....unfortunately, some images are too big now....
The "WIDTH=" or "HEIGHT=" technique changes the display size but not the size in storage or over the wire.
IrfanView will resize images off-line. Free, Windows-only. https://www.irfanview.com
Does somebody know where could I be getting that high pass filter in my circuit?
I already have the tests on almost every node of the circuit, so I can show you guys if you want!
This post is a definitive testing of my circuit, meaning it's better documented than the first one.
It's therefore an ask for help to all of you who might know anything about circuits and guitar pedals.
I'm very lost and lacking of time right now, so I would thank ANY help!
Soo I was able to test every point that I wanted today.
Remembering, this is the schematic on LTSpice (for easier visualization):
part 1 - (https://i.imgur.com/g4SWsDmh.png?1)
part 2 - (https://i.imgur.com/a06EWHvh.png?1)
And this is the official schematic (with real values) on EasyEda:
(https://i.imgur.com/UWCCPcPh.png?2)
Now, as I referred in that previous post, I was getting a very strange frequency response after some time not using/testing the Phaser Pedal (before this time everything was ok). My conclusion is that there is a high pass filter throughout the circuit (that will be proven by images show below), that I cannot understand where comes from.
Before that, let me show the frequency response I once had with my pedal:
1 - (https://i.imgur.com/ULpzxjYh.png?1)
2 - With the trimmer in different pos:
(https://i.imgur.com/ijZzyd0h.png?1)
As I referred, after some time without using the pedal, the freq response got kinda crazy:
1 - (https://i.imgur.com/zxhCTv5h.png?1)
2 - (https://i.imgur.com/iP0gNaeh.png?1)
That being said, note that "Good"="flat" and "Bad" = High Pass filter non sense (you will see below).
Output of the 2nd op amp (first of the phase shifting) is ok (zoomed in)
(https://i.postimg.cc/p95WgNWg/c.png) (https://postimg.cc/p95WgNWg)
However the inverting and non-inverting inputs of the same op amp have this same response (bad):
(https://i.postimg.cc/ZCqCVMNh/d.png) (https://postimg.cc/ZCqCVMNh)
In my head this isn't even possible..
U3, which is the capacitor, has a good freq response on the left leg, but the leg connected to the JFET has a bad freq response.. This I can't see why also.
The pos and negative inputs of the 3rd op amp are "bad" but it's output is good, just like the 2nd op amp, like (???)
Now, between U6 and R10, the freq response is good, but on the other leg of U6 it's already bad.
As for R15, which is connected to the 3rd and the 4th op amps, has a good freq response on the left side and a bad one on the right side.
Same goes for U7.
As we can conclude, the 4th op amp has a bad freq response on the output:
(https://i.postimg.cc/MXVDzX3G/e.png) (https://postimg.cc/MXVDzX3G)
The inverting and non inverting inputs of the 4th op amp have the same response..
In this matter, both legs of R14 are bad.
R8 (Vref side) and every resistance that is making the all pass filter in parallel with the JFET, has a req response looked like the output of the pedal, but attenuated. The other leg is bad.
As for the 5th op-amp, it has a bad freq resp on the non inverting input.
The output and the inverting input are also bad
Both legs of U9 Cap are bad too (which is different from the other caps).
The 6th op-amp has at the non-inverting the freq response of the output of the pedal but attenuated:
(https://i.postimg.cc/9Dm5G6wG/g.png) (https://postimg.cc/9Dm5G6wG)
Now as for the JFET's, in every drain point of every JFET, the response is bad. In the last FET the response is stabilized before the other ones:
(https://i.postimg.cc/2VTXfV3Z/h.png) (https://postimg.cc/2VTXfV3Z)
In the source and the gate the freq resp of every FET are equal. They're the same as the output of pedal but attenuated:
(https://i.postimg.cc/23YDkLjc/i.png) (https://postimg.cc/23YDkLjc)
If someone got to here and thinks he/she can help me, please say something! I'm desperate! Thank you very much
A couple of things up front:
- When you hit a place which goes bad, in your case the third stage, you are best to top there an try to fix it.
everything beyond that point can't be expect to work as the "road is blocked" by that stage.
- You should check what to expect from each point in the circuit using spice.
The points at the + input of the opamp are expected to be high-pass.
This doesn't appear on the output as circuit as a whole is wired as an all-pass filter.
- Check the DC voltages on the opamp outputs and inputs
So to start there. The things that are going to stop the third-stage behaving like an all-pass are: (EDA schem)
- R10 not connected. } In both theses cases the opamp would act like a buffer
- R11 shorted. } and the high-pass behaviour on the + input would appear on the output.
- Opamp dead. Feedback from R10 and R11 clearly will stop the design all-pass behaviour.
Beyond DC checks and checks for shorts, unless you can prove to yourself otherwise, it would be easier to simply replace the opamp for the third stage. For example if you lift the leg of the cap to R12 you would expect that stage to have a gain of -1. You can check both the gain an polarity with an oscilloscope.
Quote from: Rob Strand on November 17, 2020, 04:06:08 PM
- When you hit a place which goes bad, in your case the third stage, you are best to top there an try to fix it.
everything beyond that point can't be expect to work as the "road is blocked" by that stage.
First thank you very much for responding, Rob!
Well you are right. Actually I discovered that it's not on the 3rd stage that it starts messing up..
The 2nd op amp (1st of the phase shifting) has a bad freq response on the inverting AND non inverting inputs but the output is good, like (?) . What you're saying about the + input having this response bugs me because the - input of the 2nd also has bad freq resp (though I know you're right)...
Then the 3rd op amp has the inputs bad but the output is good, which seems even worse.
The 4th op amp also has a bad output.
QuoteYou should check what to expect from each point in the circuit using spice.
The points at the + input of the opamp are expected to be high-pass.
This doesn't appear on the output as circuit as a whole is wired as an all-pass filter.
You're absolutely right, I've become so obsessed with debugging the circuit that I forgot what it should look like in spice..
Quote- Check the DC voltages on the opamp outputs and inputs
For this matter, I've checked it dozens of times, and it is all good!
Quote
So to start there. The things that are going to stop the third-stage behaving like an all-pass are: (EDA schem)
- R10 not connected. } In both theses cases the opamp would act like a buffer
- R11 shorted. } and the high-pass behaviour on the + input would appear on the output.
- Opamp dead. Feedback from R10 and R11 clearly will stop the design all-pass behaviour.
Okk! So, following these advices, I went to check continuity (doule checking) and R10 (two sides) and R11 (two sides) are good actually.
But this could help if the problem is really at the 2nd op amp as I think it might.
Quote
Beyond DC checks and checks for shorts, unless you can prove to yourself otherwise, it would be easier to simply replace the opamp for the third stage. For example if you lift the leg of the cap to R12 you would expect that stage to have a gain of -1. You can check both the gain an polarity with an oscilloscope.
Maybe I'll do it on the 2nd op amp, idk. But right now I'm in fear of taking off components of the board...
I did continuity test on the whole PCB and power supply section, every single thing was alright except:
470k, R15, R8, R28: These ones might be badly connected and I'll re-solder them.
I just broke/destroyed one of the pads of my PCB trying to resolder the resistance R8.. What can I do now? Do I have to interrupt the other pad of the resistance and solder it directly on the point that I want? What should I do?
Note that I have a PCB with accidental smd pads (Which I didn't mean to order but messed up).
Thanks in advance
QuoteI just broke/destroyed one of the pads of my PCB trying to resolder the resistance R8.. What can I do now? Do I have to interrupt the other pad of the resistance and solder it directly on the point that I want? What should I do?
These things happen.
Use thin wire to wire the parts up directly. (The circuit won't care if the signals pass through the PCB or the wires!)
Quote from: Rob Strand on November 17, 2020, 08:43:31 PM
These things happen.
Use thin wire to wire the parts up directly. (The circuit won't care if the signals pass through the PCB or the wires!)
Yeah they sure do... Unfortunately it was the resistance R8 which I think was the problem. Anyway, I'll try to do as you say, trying not to touch other components with wire.
Btw, do you think I should do anything else ike rip off what's left of the "pad"? Also, it's a node where there's 3 components connected. If I connect one leg of R8 to for example the JFET (first component), will it also be connected to the other (capacitor)?
QuoteBtw, do you think I should do anything else ike rip off what's left of the "pad"? Also, it's a node where there's 3 components connected. If I connect one leg of R8 to for example the JFET (first component), will it also be connected to the other (capacitor)?
It depends on what damage has been done and how the PCB is routed. Just make your own judgements with your eyes. Anything that looks like it might not connect just wire it across to make sure it's connected. Even using the multimeter isn't trust worthy when intermittent connections are possible.
Quote from: Rob Strand on November 17, 2020, 10:28:19 PM
It depends on what damage has been done and how the PCB is routed. Just make your own judgements with your eyes. Anything that looks like it might not connect just wire it across to make sure it's connected. Even using the multimeter isn't trust worthy when intermittent connections are possible.
Right, that' accurate. I've checked the actual vias and paths of the PCB on EasyEda and was able to see that the Pad I lifted doesn't have any vias, it is directly connected to other component, tk god..
When you say wire it, you say wire it from the component to the desired point, even if there's a weak connection there?
Yes. Using the multimeter got me perfect connections along the whole board. However I got to see with good light and discovered some crappy ones and one that was disconnected (R15).
Now I also went to look at the freq responses on LTSpice and discovered that the bad freq resp should exist on the - and + inputs, so everything was correct. However on the 4 th op amp (3rd of phase shifting) there was a bad output, like you mentioned, and I discovered a problem between R14 and R15.. So I conclude it was always a matter of this R15 being disconected.
I already soldered it and I'll se tomorrow how the circuit behaves (of course if I can resolder the other missing connections and fix the lifted pad point)
QuoteI already soldered it and I'll se tomorrow how the circuit behaves (of course if I can resolder the other missing connections and fix the lifted pad point)
Good luck. Given it worked before it's probably only some small silly thing. I guess the problem is finding it but you should be able to narrow things down with an oscilloscope.
Quote from: Rob Strand on November 18, 2020, 07:06:13 AM
Good luck. Given it worked before it's probably only some small silly thing. I guess the problem is finding it but you should be able to narrow things down with an oscilloscope.
Thanks Rob! Yes it might be.. Given that I am soldering on smd pads, there might be more than one silly thing hahahah.
I actually was doing it with the oscilloscope of the audio precision measurement system and also by getting the frequency responses.
Anyway I'll check again around R10 and R11 as you said, there might be something there too.
Look what I had to do with R8! Hahah, soldered it directly to R27 with a little wire on the tip..
Everything is now resoldered and theoretically well connected (and visually). So tomorrow I'll see if this guy behaves good or not, and I'll make sure to let you know!
(https://i.postimg.cc/S2M3dcc8/20201118-195053.jpg) (https://postimg.cc/S2M3dcc8)
Quoteook what I had to do with R8! Hahah, soldered it directly to R27 with a little wire on the tip..
it does the job for sure.
Today's tests with Vbias on max and Vbias on min, respectively (depth and speed on minimum):
(https://i.postimg.cc/JHKzdt8K/test-19-11-vbiasmax.png) (https://postimg.cc/JHKzdt8K)
(https://i.postimg.cc/Cdpmj7Km/test-19-11-vbiasmin.png) (https://postimg.cc/Cdpmj7Km)
No possible words for the satisfaction. Thanks Rob!
QuoteNo possible words for the satisfaction. Thanks Rob!
No worries man. You did all the work ;D. Anyway good it's up and running again.
Quote from: Rob Strand on November 19, 2020, 04:52:32 AM
QuoteNo possible words for the satisfaction. Thanks Rob!
No worries man. You did all the work ;D. Anyway good it's up and running again.
I'm really very glad! You did some work too, if I had to count with only my teacher, this would probably gone bad (or not gone anywhere).
Here's some frequency responses (depth min) with some comments:
(https://i.postimg.cc/svDtYdP4/teste-19-11-duvida1.png) (https://postimg.cc/svDtYdP4)
Why should the left notch be less attenuated than the right? I don't know, maybe my high pass filter..
(https://i.postimg.cc/S2kZmCDf/teste-19-11-duvida2.png) (https://postimg.cc/S2kZmCDf)
(https://i.postimg.cc/hhJmfh6L/teste-19-11-duvida4.png) (https://postimg.cc/hhJmfh6L)
This flatness could be explained by the LFO varying a little bit even with the depth on min? Or should I be putting more test points to make it more accurate? Or smth else?
(https://i.postimg.cc/4Y4NHSyD/teste-19-11-duvida5.png) (https://postimg.cc/4Y4NHSyD)
The middle of the spectrum seems to have more uniformity on the attenuation of the notches..
(https://i.postimg.cc/tY44YcYL/teste-19-11-duvida6.png) (https://postimg.cc/tY44YcYL)
This is with the feedback on the maximum value. Is it normal that the attenuation on the notches is less than without feedback? Or can I remediate it?
These are not very urgent questions btw, the circuit is working, and for sure my teacher accepts this like it is.
QuoteWhy should the left notch be less attenuated than the right? I don't know, maybe my high pass filter..
This flatness could be explained by the LFO varying a little bit even with the depth on min? Or should I be putting more test points to make it more accurate? Or smth else?
If you look closely at the plot the curves aren't smooth. The curve is made up of lines joining together. If the lines just happen to join at the middle of a notch you will see a deep notch. If the line joins each side of the notch you will see a chopped-off notch. You can see this in your second plot.
The problem should be fixable by just changing the plotting or FFT settings. It's normal for FFTs to have a certain resolution which is set by how long you look at the waveform. If the sample rate is high and the number of points is fixed then you don't look at the waveform very long. So what you have to do is reduce the sample rate. FFT resolution affect the low frequencies since a step of 10Hz at 50Hz is more jagged than a 10Hz step at 1kHz.
*However* in your case it might be a different problem because I can see there is jaggedness at 400Hz with wider frequency steps than at 40Hz. So the jaggness has the same to the eye on the screen. To me I'd be looking a the plot settings more than the FFT. See if you can find the plot resolution or number of plot points. (It still could be the FFT settings if the equipment is using a log-spaced FFT, although this isn't very common.)
QuoteThis is with the feedback on the maximum value. Is it normal that the attenuation on the notches is less than without feedback? Or can I remediate it?
Feedback *does* mess with the notches. As it turns out it's not the feedback itself that affects the circuit. It's the way feedback is added to the circuit. The 24k (or 22k) feedback resistor affects the way the all-pass filter works. If for example you added an opamp just to do the feedback, so all of the all-pass filters are identical, you will see different a behaviour. The way to check that would be in spice.
Just smth before we continue the previous subject. I am using this circuit to power up my pedal (with battery or DC jack switching when one is connected and other is not, you know):
(https://i.postimg.cc/8sRhM59Y/tonepad-Rob.png) (https://postimg.cc/8sRhM59Y)
Now, I am trying to make this work for ages, and for some reason it always refused to turn on the power with my battery (I've tried messing with the 6.3 input connector being connected or not; using only the battery; checking the connections; checking thousand times what are the pinouts of my 6.3 jack connector to make sure I don't make mistakes, etc).
For some godly reason, I happened to touch the battery - on the ground when the + was already connected to the switch, and IT WORKED!
So I'm thinking two things:
- The circuit I'm copying is wrong;
- I might be confusing the pinouts on the 6.3 connector
If the circuit is wrong, maybe what should be in place of the - battery on the ring is that - connected to the groud point of the DC switch and then on the ring, as some circuits on the internet suggest, am I right? I sincerely hope..
Quote from: Rob Strand on November 19, 2020, 05:36:12 PM
If you look closely at the plot the curves aren't smooth...
...You can see this in your second plot.
True! I must try to change the number of points, and see if it helps..
Quote
*However* in your case it might be a different problem because I can see there is jaggedness at 400Hz with wider frequency steps than at 40Hz...
... (It still could be the FFT settings if the equipment is using a log-spaced FFT, although this isn't very common.)
What do you mean with "So the jaggness has the same to the eye on the screen." ?
Anyway I'll try messing with the plot ponts and if it doesn't help, I'll go and try to mess with the FFT!
Quote
Feedback *does* mess with the notches...
...The way to check that would be in spice.
Pretty interesting! I might give it a try in Spice because I'll have to explain the working of the feedback as it is, so it would surely help.
I understand that it does affect the all pass working, because it is putting output signal on the - input of the 3rd all pass stage, so it's kinda amplifying what was in between notches.
QuoteSo I'm thinking two things:
- The circuit I'm copying is wrong;
- I might be confusing the pinouts on the 6.3 connector
It looks OK to me.
Confusing the pins won't help.
Try using a multimeter and check if the battery connect through or not. No need to power up anything but you can plug the plugs in and out to see what connect and what disconnects.
QuoteWhat do you mean with "So the jaggness has the same to the eye on the screen." ?
Anyway I'll try messing with the plot ponts and if it doesn't help, I'll go and try to mess with the FFT!
The plotted curve is made up of lines. Normally if it's the FFT the lines a longer (causing it to be jaggered) at low frequencies and closer together at high frequencies (smoother). However on your plot the lines seem to be roughly the same length across all frequencies. That looks like a plotting problem. If I look close it even looks like the curved part has short lines - that's something automatic plotting can do - the problem is all the lines need to be shorter to smooth out the curve.
QuotePretty interesting! I might give it a try in Spice because I'll have to explain the working of the feedback as it is, so it would surely help.
I understand that it does affect the all pass working, because it is putting output signal on the - input of the 3rd all pass stage, so it's kinda amplifying what was in between notches.
It's worse than that. Even with a separate opamp you get signal from the output. That's kind of the point of adding feedback. However, if you grounded the side of the 24k/22k resistor that goes to the output (maybe through a cap so the DC doesn't get stuffed up) there will be no feedback but the all-pass filter with the 24k/22k doesn't work the same as if you removed the 24k/22k altogether.
Quote
Try using a multimeter and check if the battery connect through or not. No need to power up anything but you can plug the plugs in and out to see what connect and what disconnects.
Ohh you're right, I've not done that with the battery connected there yet...
Anyway here's a picture of the exact 6.3 jack I'm using:
(https://i.postimg.cc/G81ts4th/Edited-20201120-132549.jpg) (https://postimg.cc/G81ts4th)
I'll try to explain what I think it works:
There are three lugs "together," and one lug connected on the other side. This one separate lug I tried to understand where it connects and didn't arrive at a good conclusion, so I chopped it off.
Of the 3 remaining lugs:
-Lug on the left: ground
-lug in middle: ring
-lug on right: tip
Now for the" 3 big legs":
-big one on the left: tip
-small one touching the big: ring
-the big on the other side: ground
Hope I'm right because it's already soldered hahahah (works with 9V transformer)
Quote
The plotted curve is made up of lines...
... the problem is all the lines need to be shorter to smooth out the curve.
Yes, makes total sense. Later today I'll be able to tell you some kind of conclusion around this as I'll be around the APX.
Oh and one more thing: my pedal is working well with the guitar connected. BUT there's always a BUT and this time the BUT is that on the output I can hear clicking that have a constant cycle (that changes when I change the speed pot). Also when it is discomnected (true bypassed) the clicks continue (but more attenuated).
I know they are from The LFO, because it theoretically makes triangle waves all the time (non stop) but I don't know how to fix this.. Maybe low pass filtering with a sharper curve, or should there be another way to fix this?
The LFO has frequencies of 0.3 Hz to 8 Hz aproximattely.
Quote from: savethewhales on November 20, 2020, 08:35:38 AM
There are three lugs "together," and one lug connected on the other side. This one separate lug I tried to understand where it connects and didn't arrive at a good conclusion, so I chopped it off.
The "separate" lug appears to be the screen connection, so removing it wasn't a good idea. It's easy enough to work out which lug is connected to which connection using a DMM. Having an extra switch connection isn't helping. Try to find stereo jacks in future with only three connections.
Quote
The "separate" lug appears to be the screen connection, so removing it wasn't a good idea. It's easy enough to work out which lug is connected to which connection using a DMM. Having an extra switch connection isn't helping. Try to find stereo jacks in future with only three connections.
Exactly!!! That is sold as a stereo 6.3 socket. But with the multimeter I've tried but couldn't find where it connects, except for where it is touching, as we can see on the image. If that wasn't yet chopped, I wouldn't use it anyway..
Anyway am I thinking right about the connections of the other lugs?
I just wonder what the hell is happening. Maybe I'll have to buy another 6.3 stereo socket, but a good one this time, and hope it works.
If you can't determine with your multimeter what lug connects to what part of a plug, then you need a new multimeter too.
As for the lugs you left behind, the one in the middle (it's a bit smaller than the others) is connected to the useless switch contact. This was the one to remove. The furthest one in the picture connects to the tip. That leaves the nearest lug which must connect to the ring.
Quote from: bluebunny on November 20, 2020, 12:08:09 PM
If you can't determine with your multimeter what lug connects to what part of a plug, then you need a new multimeter too.
As for the lugs you left behind, the one in the middle (it's a bit smaller than the others) is connected to the useless switch contact. This was the one to remove. The furthest one in the picture connects to the tip. That leaves the nearest lug which must connect to the ring.
Hmm alright! What about the sleeve?
I tried, with the multimeter, connecting the battery and seeing where it connected. The middle lug (which you say connects to the useless switch), connected to the "leg close to the tip", which disconnects from the tip when the input jack is inserted.
Quote from: savethewhales on November 20, 2020, 01:12:22 PM
Hmm alright! What about the sleeve?
I tried, with the multimeter, connecting the battery and seeing where it connected. The middle lug (which you say connects to the useless switch), connected to the "leg close to the tip", which disconnects from the tip when the input jack is inserted.
The "sleeve" (i.e. screen) connection is the lug you cut off.
Forget a battery for the moment. Also forget that smaller middle lug. Put your multimeter on a continuity or resistance setting. Put one probe on one of the other lugs you have left, and leave it there. Now touch each of the two springy contacts (that would make contact to a plug if one were inserted) to find out the correspondence between lug and contact. Repeat for the other lug.
TBH, you're only going to get so far with a butchered stereo jack. Just throw it out and replace it with a new one.
I am sorry for taking too long to post, it's because the pedal worked 100% and I ended up staying more time on my university to make all the needing tests. In the end I came home too late for posting right after.
Quote from: bluebunny on November 20, 2020, 04:46:18 PM
The "sleeve" (i.e. screen) connection is the lug you cut off...
...Just throw it out and replace it with a new one.
I tested it with the multimeter and the middle one goes to the biggest "lug" which is touching the tip when the jack isn't connected. Anyway this is confusing me a hell of a lot. After I'm done writing the report (final project from college), I will go and buy a good stereo jack and see if it works. If not, bye bye battery.
Now for the pedal behaviour itself, those clicks I was mentioning before were happening when the box wasn't closed, it was kind of the skeleton of the pedal yet. So it was happening a problem of grounding I believe, because:
1 - The frequency response, as I put here before in a post, was actually flat where the notches don't exist and there was no trace of clicking problem;
2 - When I closed it, the clicking was way better or didn't even exist. If I tried, I would hear it, but whenever I'm playing the guitar, the noise disappears. So I guess the "grounding" is way better now (not perfect yet).
About the resolution of the plots, I was able to test with more points and saw that with the problem of the squared curve disappeared/diminished a lot when testing with more points. Nevermind the scale of the graph or size of the image:
With 60 plot points:
(https://i.postimg.cc/23HD9jjw/Rob-1.png) (https://postimg.cc/23HD9jjw)
With 200 plot points (the maximum I could because it takes too long):
(https://i.postimg.cc/LYYtd8K1/rob-2-teste-caixa-depthmin-feedmin.png) (https://postimg.cc/LYYtd8K1)
Hello!
I'm having some oddities with my LFO.
Here's the circuit I'm using:
(https://i.postimg.cc/nXgFgn46/LFO-25-11.png) (https://postimg.cc/nXgFgn46)
And this is the response I'm having at the input of the JEFT gates with the minimum LFO frequency:
(https://i.postimg.cc/CBYgp5z6/TEK0015.png) (https://postimg.cc/CBYgp5z6)
I didn't get this response when I was designing the circuit or testing in breadboard, so that's why I'm finding it strange..
Below there's the reponse with the maximum LFO frequency.
(https://i.postimg.cc/Z947Tdx3/TEK0010-3.png) (https://postimg.cc/Z947Tdx3)
It's good! I don't know why it changes so much between this frequency and the lower freq.. I'm guessing duty cycle, but then, shouldn't that strange wave be the higher frequency one, because there wouldn't be enough time for it to complete the integration?
Also, I don't know where these strange clicks come from:
(https://i.postimg.cc/ZCLjwRS5/TEK0006-3.png) (https://postimg.cc/ZCLjwRS5)
I'm also seeing a change on the offsets and the range on the different LFO frequencies without even changing anything besides the speed:
(https://i.postimg.cc/DWhXHQPV/TEK0013.png) (https://postimg.cc/DWhXHQPV)
(https://i.postimg.cc/kVwBH058/TEK0014.png) (https://postimg.cc/kVwBH058)
What's going on here? How can I have the same offsets, same voltage range and same waveform independently of the frequency? Thank you very much for your attention!
QuoteAnd this is the response I'm having at the input of the JEFT gates with the minimum LFO frequency:
I'd be thinking losses in the electrolytic caps 100uF+ 10uF. Maybe one is in the wrong way. Maybe they are different parts (brand type) to the ones you previously tested.
QuoteWhat's going on here? How can I have the same offsets, same voltage range and same waveform independently of the frequency?
One of the electrolytic caps around the wrong way might do it. So too could be the fact to are using two different values in series.
I think both of these problems *could* be related to the electrolytic caps.
QuoteAlso, I don't know where these strange clicks come from:
Ticks are fairly common with circuits that have an LFO.
I'd say two common causes would be:
- using dual/quad opamps where different opamps in the same package are used for audio and for the LFO.
- Not enough bypassing on the supply at the LFO. Try adding, even temporarily, a 100uF cap across the pins of the LFO (specifically the Schmitt trigger opamp). If that doesn't work the next step is to put a resistor between the main power and the power for the LFO circuit. Something like 10ohms to 100 ohm. You will need to keep the 100uF cap on the LFO power. The idea here is to isolate the LFO power.
There's other possibilities like the LFO wiring is near or touching audio wires in the enclosure, PCB tracks on the LFO are close to audio tracks. Ground tracks sharing LFO and audio signals.
Another one is the LFO is causing fluctuations on Vref or Vbias and that is injecting click into the audio; as the any variations in Vref will appear at the audio output.
Quote
I'd be thinking losses in the electrolytic caps 100uF+ 10uF. Maybe one is in the wrong way. Maybe they are different parts (brand type) to the ones you previously tested.
Ok. I think the ways of both are correct: Reversed to each other. However I think I used (as far as I remember) the exact same caps as I am using now on the circuit. In a first stage of testing I used a single cap with a different value, but I think I remember testing with these two the way they are now.
Quote
One of the electrolytic caps around the wrong way might do it. So too could be the fact to are using two different values in series.
I think both of these problems *could* be related to the electrolytic caps.
Hm... I get it. It all comes down to the 2 electrolytic in reverse series.. Which is something I didn't want to happen because I can't really explain how they work, except for saying that this is widely used.
Again, I'm 99% sure they are the right way. But on saturday I'll open the circuit and check that. It's just I do'nt want to hang with the open circuit till there..
Anyway here goes the real schematic on EasyEda:
(https://i.postimg.cc/Bjq6Bw1X/important-easy-eda-2.png) (https://postimg.cc/Bjq6Bw1X)
We can see that they are in the right direction, but let's see if I didn't screw up on assemblying.
Quote
Ticks are fairly common with circuits that have an LFO.
I'd say two common causes would be:
- using dual/quad opamps where different opamps in the same package are used for audio and for the LFO.
I think there is no dual op amp here used for LFO and audio at the same time, as far as I see on the EasyEda schematic..
Quote
- Not enough bypassing on the supply at the LFO. Try adding, even temporarily, a 100uF cap across the pins of the LFO (specifically the Schmitt trigger opamp). If that doesn't work the next step is to put a resistor between the main power and the power for the LFO circuit. Something like 10ohms to 100 ohm. You will need to keep the 100uF cap on the LFO power. The idea here is to isolate the LFO power.
Fair enough.. it seems something like the P90 LFO that has that capacitor and that resistor that you said were just controlling the rises/falls of the schmitt trigger (that weren' that important). I guess I'll do it on the LTSpice simulation, because my circuit is already soldered. I would just solder anything on top if I were sure that it would work. If not, I'm afraid of damaging the circuit.
Just for the record, what's the "main power" and the "LFO power"?
Quote
There's other possibilities like the LFO wiring is near or touching audio wires in the enclosure, PCB tracks on the LFO are close to audio tracks. Ground tracks sharing LFO and audio signals.
Interesting cause ground tracks most probably are the same.. But the wiring seems to be correct, even though I will double check it.
Quote
Another one is the LFO is causing fluctuations on Vref or Vbias and that is injecting click into the audio; as the any variations in Vref will appear at the audio output.
This is what used to happen in the P90 LFO, in the simulations actually. I tried to isolate the parts as much as I could with all those op amps on the LFO for this not to happen but I guess it's not that easy after all.
QuoteHm... I get it. It all comes down to the 2 electrolytic in reverse series.. Which is something I didn't want to happen because I can't really explain how they work, except for saying that this is widely used.
I guess one thing that's not common is putting two different values in reverse series. It kind of asking to expose the complexities of putting electrolytics in series. Why not just use two of the same values? You might need to experiment with the value to get the same LFO frequency.
As far as debugging the problem, it could be worthwhile replacing the two electro's with equal values anyway.
I could speculate that when you built the circuit it did work fine but after testing for long periods the one of the caps has lost its oxide and gone leaky.
Quote
Fair enough.. it seems something like the P90 LFO that has that capacitor and that resistor that you said were just controlling the rises/falls of the schmitt trigger (that weren' that important). I guess I'll do it on the LTSpice simulation, because my circuit is already soldered. I would just solder anything on top if I were sure that it would work. If not, I'm afraid of damaging the circuit.
Just for the record, what's the "main power" and the "LFO power"?
Yes, that's another trick. It can also be used on a circuit like yours. Checkout C26 and R38 on the Boss BF2 Flanger,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
QuoteInteresting cause ground tracks most probably are the same.. But the wiring seems to be correct, even though I will double check it.
Putting a big cap across the LFO/Schmitt trigger opamp power rails can help here as well. It keeps the LFO current pulses local to the LFO opamp and cap and stops the pulse going down the ground tracks.
Best to concentrate on the power rail caps stuff first since that's probably the most common fix.
QuoteI guess one thing that's not common is putting two different values in reverse series. It kind of asking to expose the complexities of putting electrolytics in series. Why not just use two of the same values? You might need to experiment with the value to get the same LFO frequency.
As far as debugging the problem, it could be worthwhile replacing the two electro's with equal values anyway.
Yeah that's right.. It was because I didn't even had the right values of electrolytics caps to do this method (not even worth mentioning the non-polarized). In that way I was left with a 100uF and a 10uF.
It could be causing those problems but actually the equivalent capacitance is equal to 9.09 uF as the simulation on Spice agrees with real life testing.
Quote
I could speculate that when you built the circuit it did work fine but after testing for long periods the one of the caps has lost its oxide and gone leaky.
I thought something like this but.. it was only one week.. how is it possible?
Quote
Yes, that's another trick. It can also be used on a circuit like yours. Checkout C26 and R38 on the Boss BF2 Flanger,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
Sure.. it's the exact same from the P90 circuit.
Quote
Putting a big cap across the LFO/Schmitt trigger opamp power rails can help here as well. It keeps the LFO current pulses local to the LFO opamp and cap and stops the pulse going down the ground tracks.
Best to concentrate on the power rail caps stuff first since that's probably the most common fix.
Nice!!! You talk about connecting the big cap literally to the 9V and 0V points of the op amp?
QuoteI thought something like this but.. it was only one week.. how is it possible?
I do suspect it's leakage, and it's likely to be caused by using two different cap values, but the detailed cause is a lot of speculation. Some caps are likely to be more prone to problems than others.
o bad again.
If you replace the caps with two equal values and it all works then you can just move on
If you want to know why that's a separate project. You could put the two caps on a DC supply to re-plate them. Look up electrolytic capacitor "reforming". That's only going to confirm the problem. It won't fix the cause. The caps could, and maybe will, go bad again.
QuoteNice!!! You talk about connecting the big cap literally to the 9V and 0V points of the op amp?
Yes just solder it across. Sticking big caps across the power rails is a quick way to narrow down many problems. It stops the need to think of more crazy ideas.
I am very sorry for taking this long.. I'm writing down the project, being awake till 3h30 morning every day, so as this wasn't a very urgent subject (because the pedal works still), I didn't went to look further on it.
Quote
I do suspect it's leakage, and it's likely to be caused by using two different cap values, but the detailed cause is a lot of speculation. Some caps are likely to be more prone to problems than others.
o bad again.
If you replace the caps with two equal values and it all works then you can just move on
Unfortunately I'm unable to do this now.. I guess I'll accept it.. It's not audible on the pedal anyway (if it was I would for sure desolder and try to fit one new non polarized cap there).
Quote
If you want to know why that's a separate project. You could put the two caps on a DC supply to re-plate them. Look up electrolytic capacitor "reforming". That's only going to confirm the problem. It won't fix the cause. The caps could, and maybe will, go bad again.
Ok.. thanks!
Quote
Yes just solder it across. Sticking big caps across the power rails is a quick way to narrow down many problems. It stops the need to think of more crazy ideas.
For sure this was something I could have done but totally forgot to do it while there was time, and now (and for some time) I don't seem to have time to do it. If the pedal works, screw this for now.
Hello everyone! This is the part of the circuit that represents the LFO:
(https://i.postimg.cc/fJF73JVM/LFO-4-12.png) (https://postimg.cc/fJF73JVM)
NOTE: that the integrator caps are like they are for a matter of showing what I build into the PCB, but the equivalent cap value should be around 9 and 10 uF for the calculations. Also, R32 is a 500k potentiometer and Vref sits at 4.78 Volt.
Now, while I was searching for the integrator cap and resistor values, I did simulations, no math. In that manner I was able to get the frequencies I wanted, between aproximately 7 Hz and 0.3 Hz. I'm writing my project down and I needed to know what are the equations for the frequency of the LFO.. Can someone help me? I've searched online and what I found didn't give me a reasonable answer (when I would calculate, it would always give me like 14 Hz or 0.05 Hz, with these values, which is far from the measurement and the Spice simulations).
Thank you very much, cheers,
Fred
Hello!! Please ignore my last post (I couldn't find the modify button to erase it).
So this is part of my final phasing circuit:
(https://i.postimg.cc/c6v2CSj3/circ-final.png) (https://postimg.cc/c6v2CSj3)
Here at the start, R3, C1 and R4 serve to make a high pass filter on the frequency of 7.13 Hz. Also 470 kohm helps getting the input impedance high enough for a pedal.
However I took strong inspiration on the P90 LFO and ended up putting the 470 kohm connected to Vreference (which is the fixed voltage coming from the Zener). But I don't actually know why it's done like that (the connection to Vref).. I imagine it's like a coupling? But why do I need to make a coupling at the start of the circuit?
This is what most bugged me at the time of designing the circuit but I just accepted the fact then.. If somebody could help me I'd be very much thankful.
Cheers, Fred
> why it's done like that (the connection to Vref)..]
The power is zero and +9V, right?
But audio swings both ways around "zero". How can the amp do that?
Our usual trick is to "bias" the amplifier DC condition to "about half of supply". Now audio can swing both ways. At the output another cap re-references to zero volts DC.
Is that what you are asking?
Quote
Is that what you are asking?
Exactly! Thanks!
So what the 470 kohm really makes is getting the non inverting input of U6 to being Vref right?
So I got 17 out of 20 in my project of the phaser pedal.. I am very very happy about this!!!
Just have to thank specifically:
- Rob Strand
- PRR
- Everyone that helped me throughout this project (Eb7+9 - JCM, 11-90-an, bluebunny, others)