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DIY Stompboxes => Building your own stompbox => Topic started by: edvard on January 12, 2025, 02:57:46 AM

Title: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 12, 2025, 02:57:46 AM
... it lowers the headrooom.

There, I said it.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: FiveseveN on January 12, 2025, 04:29:03 AM
(https://i.imgflip.com/9gezb5.jpg)
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: PRR on January 12, 2025, 04:45:32 PM
Quote from: edvard on January 12, 2025, 02:57:46 AMdoes not increase the gain... it lowers the headrooom.

What is the difference?

(https://i.postimg.cc/xqpQcd3K/CMOS-gain.gif) (https://postimg.cc/xqpQcd3K)
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 12, 2025, 09:50:38 PM
Quote from: FiveseveN on January 12, 2025, 04:29:03 AM(https://i.imgflip.com/9gezb5.jpg)

Admittedly, I just did a few off-the-cuff simulations in LTspice, two lines of standard CMOS inverter (pmos/nmos totem pole like in the datasheets) wired for linear via 10k/100k for 10x (ha!) gain, and both powered by their own voltage supply.  I made the supply voltages 7.5V and 15V, and set the sine wave generators at 0.1V so I could get clean sine waves on the output. The traces were almost exactly the same. 

OK, the lower supply voltage one read ~63.9mv more on the peak, so maybe everyone is right, but not enough to make an audible difference when overdriving the things, which is what people usually mean when they say "gain" on a dirt box.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 12, 2025, 10:49:55 PM
Quote from: PRR on January 12, 2025, 04:45:32 PM
Quote from: edvard on January 12, 2025, 02:57:46 AMdoes not increase the gain... it lowers the headrooom.

What is the difference?

(https://i.postimg.cc/xqpQcd3K/CMOS-gain.gif) (https://postimg.cc/xqpQcd3K)


Good question.  Increase gain to collide with the headroom, or lower the headroom until you crash into the signal, it's all going to sound the same in the end, just one will have a higher amplitude to deal with at the back door.

This all started because I've heard more than one experimenter proclaim it as established fact that running a 4069 at lower voltage would produce more gain, and therefore more distortion, therefore more rock 'n roll.  I couldn't help but think "but isn't it possible that the distortion you're hearing is actually due to reduced headroom?"
So I got curious.   
My next thought was that with the gain going up as the supply voltage came down, there's gotta be a "sweet spot" somewhere in there where the noise floor/clipped signal ratio would be minimal.  Then, clipping the signal further (rock and rooooollll!!) would simply be a matter of pre-amplification into the inverter, reducing noise floor concerns, which you definitely have when working with high gains in CMOS circuits. 

In the end, my experiments with LTspice in regards to headroom clipping proved me mostly right, so I still say the clipping effects from reduced headroom are FAR more effective at producing distortion than any intrinsic gain induced from lowered supply voltage, but I'm still chasing noise floor nirvana.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: FiveseveN on January 13, 2025, 04:17:13 AM
Quote from: edvard on January 12, 2025, 09:50:38 PMwhich is what people usually mean when they say "gain" on a dirt box.
The fact that it's popular among the uninformed does not make it correct.

QuoteIn the end, my experiments with LTspice in regards to headroom clipping proved me mostly right
Your experiment is based on a false premise. We're talking about open loop gain here. x10 is not going to show you anything significant:

(https://i.postimg.cc/8c12hytq/cmosgain.png)

If you want to get to the bottom of this, put an actual 4049 on a breadboard, set it for open loop, feed it a ramping signal and observe the slope and headroom at different VCC.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Fancy Lime on January 13, 2025, 06:00:15 AM
Some misconception detected. The gain that changes with supply voltege is the "open loop gain", which is what you get with no negative feedback. In your test, you set the gain to 10x via a negative feedback loop. In this setup, the gain is not affected by the supply voltage because your set gain is lower than the open loop gain of the device. So in your case and some actual CMOS designs the lowering of the headroom by decreased supply voltage is indeed all that mattes. It may be enlightening to repeat your test with the gain set to 100x and 1000x.

Andy


p.s. Damn, I should not reply to posts without first refreshing the page to see if the someone has given the same answer already. So, yeah, what 57 said.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Nasse on January 13, 2025, 11:44:20 AM
I thought 50 is typical value. Sure once I tried a trick from british electronic magazine, took voltage for 4049 from viper of potentiometer, was soo long ago, but was useful if I remeber
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Nasse on January 13, 2025, 11:55:46 AM

(https://i.postimg.cc/zVK31fmn/Tonninseteli.jpg) (https://postimg.cc/zVK31fmn)
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Fancy Lime on January 13, 2025, 04:36:32 PM
Quote from: Nasse on January 13, 2025, 11:55:46 AM(https://i.postimg.cc/zVK31fmn/Tonninseteli.jpg) (https://postimg.cc/zVK31fmn)

Oh my god, I did not know the Tonnin Seteli sketch until just now. That is absolutely glorious. Watched it inbetween coverage of the devastation in LA. Necessary to give your brain a brief escape from shitty reality regularly.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 21, 2025, 10:40:31 PM
Sorry folks, had a busy and emotionally grueling week.  OK, where were we?

Aha... I see.  Open loop gain.  Got it.  It's a fact.  No disputes there, and thanks for the curves.

Here's the counterpoint that I was trying to make, but didn't have the phraseology to bloviate correctly on the subject until you wonderful folks schooled me on what the deal really was (much appreciated, really):

Open Loop Gain apparently doesn't matter a whole heck of a lot when "Gain" is what most folks call the knob on their dirt box that actuates an increase in the amplitude of a driving signal into a device whose supporting circuitry is designed to force said device to operate past its linear operation capabilities.  The resulting Rock & Roll is now burned into the cognition of a vast swath of the populace as that noise that occurs as a result of turning said knob clockwise (as engineeringly incorrect as that may be).  Precious few of said "dirt boxes" operate with Open Loop Gain in mind, unless of course it's a kinda sorta fuzz that operates via triggering square waves or some such, like Craig Anderton's "Ultra Fuzz" or Tim Escobedo's "PWM Fuzz".

Now, there's an idea; make a gated fuzz out of CMOS inverters, but the "Volume" control actually varies the power supply to the inverter chip. That'll prove the point better than your average Josephus splicing a resistor into the power supply line to "increase the gain" of some variety of CMOS-inverter-based dirt box circuit (which happens far more often, in my humble observation).

TL;DR: Decreasing the voltage supply of a CMOS inverter will increase the Open Loop Gain, not the Linear Amplifier Operation gain, which is set by a resistor network.  I feel I had to make this point because I have observed more than one stompboxian, while experimenting with CMOS inverters-as-amps, state the opinion that the former affects the latter in a meaningful way.  It does not; it simply reduces the linear "headroom" (which, conversely, DOES apparently increase the Rock & Roll.)

There, I said it.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 21, 2025, 11:26:52 PM
Hey now, actually you said something I found very useful to prognosticate on, so take all the credit due.  I bold-ed the good part:

Quote from: Fancy Lime on January 13, 2025, 06:00:15 AMSome misconception detected. The gain that changes with supply voltege is the "open loop gain", which is what you get with no negative feedback. In your test, you set the gain to 10x via a negative feedback loop. In this setup, the gain is not affected by the supply voltage because your set gain is lower than the open loop gain of the device. So in your case and some actual CMOS designs the lowering of the headroom by decreased supply voltage is indeed all that matters. It may be enlightening to repeat your test with the gain set to 100x and 1000x.

Andy


p.s. Damn, I should not reply to posts without first refreshing the page to see if the someone has given the same answer already. So, yeah, what 57 said.

Well said.  I was just trying to clear up some misconceptions I thought I had discovered, but was missing some info.  Well, some very KEY info, but you get it.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: FiveseveN on January 22, 2025, 03:01:42 AM
Quote from: edvard on January 21, 2025, 10:40:31 PMPrecious few of said "dirt boxes" operate with Open Loop Gain in mind, unless of course it's a kinda sorta fuzz that operates via triggering square waves or some such
One of the flavors in my Infinity uses no feedback for the last stage of a 4-stage CMOS drive:

(1:33—1:40)
Doesn't sound fuzzy to me, that's more of a matter of filtering.
There also happens to be an open loop op amp flavor in there that can also be set for chug or fuzz depending on one's choice of input filtering.
If you want a gated fuzz, positive feedback for hysteresis will get you there. See Parasit Studio Arcadiator (https://www.parasitstudio.se/uploads/2/4/4/9/2449159/arcadiator_3_doc.pdf) and others.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: PRR on January 22, 2025, 05:52:56 PM
Note that at 3V the DC gain is high but drops above 300Hz, so is a boomy muffled "gain", not a soprano-solo "gain".
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Nasse on January 22, 2025, 11:29:32 PM
Used to have a paper from 70s I found in dumpster that said around 10 volts is "best" for hifi use and near data sheet upper value chip get too hot. Perhaps something about thermal noise and magig smoke coming out and batteries were expensive then like today. Around 5 volts was the peak but so does output impedance up nastily and gain/bandwith gets hit by inflation. No supply noise rejection there in inverter, but opposite, you could use supply as other input or take feedback there
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on January 23, 2025, 05:33:11 AM
Hi

Back in 1980 there was this Swedish amplifier called U66 and the design of it was outlined in a Swedish electronics magazine.
The preamp was built almost entirely with Hex Inverter CD4069 used as linear amplifier. This article included a discussion of which gates could be used as linear amplifiers, eg NAND gates by connecting their inputs to one and its amplification expression for open loop gain and closed loop gain hence the marginal as well as gain dependence on power supply voltage. The designers had then chosen 12V based on the bandwidth needed for marginal.
There was also a graph that showed that when the chip was powered by 5V it had high open loop gain but only at low frequencies.
Open Loop Bandwidth increased as supply voltage was raised at 12V Open Loop Bandwidth was sufficient for some marginal for linear application and because of the the low Open Loop Gain the gain equation became very complicated ( somewhat similar to making voltage feedback with triodes) but the argument was that large marginal like in an OP wasn't needed and that instead lower order distortion was preferred. Of course at 7KHz and above the marginal was low but it was tolerated because of the more gradual onset of distortion. U66 had a power amp of about 60Ws made with discrete BJTs, The sounds it produced was more what the elder musicians at the time wanted; smooth


Have fun
Bjorn Juhl
BJF Electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: fryingpan on January 23, 2025, 06:34:58 AM
From what I remember, there is a different characteristic curve (waveshaping) at higher voltages. The higher the voltage, the "smoother" the curve. At low voltages CMOS inverters clip hard.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: fryingpan on January 23, 2025, 06:48:01 AM
Anyway, CMOS inverters are kinda noisy. They are quick and easy to use, as well as predictable, but they do come with a lot of drawbacks. IIRC, the upper threshold for voltage supply at linear operation is basically 9-10V, so headroom is what it is anyway.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on January 24, 2025, 07:07:54 AM
Hi

Somewhat historically
At the time of U66 the CD4xxx series was fairly new. I think the magazine article was from 1979 but I met an elder musician in the subway that
let me listen to a recording from his rehearsal as he was very excited that someone as young as I knew some technical aspects of his fine amp and he was also so excited how smooth his amp sounded.
Sound of tubes was very much the thing at the time but there were plethora of solutions advocated.
CD 4069 at the time was internally each inverter just two transistors in totem pole fashion. It follows that if you made feedback with a resistor input and output would rest at half Udd.
Later CD 4XXX series got several protection systems that would make the above statement invalid as some DC biasing would be required with more modern chips to make them rest at half UDD.
Compared to OP amps that have extreme gain at low frequencies typically falling at a rate of 6dB per octave and then negative feedback  trades gain for larger bandwidth and lowered distortion, higher IZ and lower Oz and other qualities this could be done to some extent with inverters at the time but more interestingly if you set the UDD ( supply voltage) you could directly control the Open Loop Bandwidth Gain and you could set it so that OLBG would be fairly low ( compared to an OP amp) but extend flat through audio bandwidth and have corner frequency above 10Khz. This would be similar to behaviour of a triode. The low Open Loop Gain would of course not let you trade much and especially if you drew close to max closed loop gain but the simplicity of the internal structure would give rise to far fewer distortion mechanisms than in an OP amp again more like a triode. So what you would get be a linear amplifier with low closed loop gain ( about 20dB maximum ) and low open loop gain. This makes closed loop amplification expression a rather complicated computation which is a slight drawback further complicated by source impedance entering the gain equation , but the simplicity of internal structure and the fact that open loop bandwidth would be a straight line would primarily make low order distortion. At overload by a sine wave input output wave form would be that of a square wave with gently rounded corners; slew rate limiting but special case indicating low order distortion mainly. This looked very much like the in Guitar Player Magazine of 1979 presented article of desired wave form by musicians from a measurement taken on a tube amp running at power amp distortion.There were competing solutions using germanium diodes, transformers, germanium transistors to name a few
As a side note there is a tech in Florida that collects waveforms of amps owned and used by famous guitarists and very common waveforms specifically on Marshalls was rather a square with a leading edge as you would see on scope highness filtering a square wave.
I suppose to this day is the question of the most desired waveforms the output of guitar amplifiers is a lost cause since there almost could be as many as there are guitarists while there are some fairly universally however contradicting answers.

Let ´s proceed on whatever sounds good ;)

Have fun
Bjorn Juhl
BJF electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: PRR on January 25, 2025, 12:23:07 AM
Quote from: BJF on January 24, 2025, 07:07:54 AMAt the time of U66 the CD4xxx series was fairly new. I think the magazine article was from 1979

Trying to organize my bad memory:

"CMOS was commercialised by RCA in the late 1960s. RCA adopted CMOS for the design of integrated circuits (ICs), developing CMOS circuits for an Air Force computer in 1965 and then a 288-bit CMOS SRAM memory chip in 1968. RCA also used CMOS for its 4000-series integrated circuits in 1968,...."
(https://images.computerhistory.org/siliconengine/1963-1-1.jpg)
"By the late 1970s, NMOS microprocessors had overtaken PMOS processors. CMOS microprocessors were introduced in 1975, with the Intersil 6100, and RCA CDP 1801. However, CMOS processors did not become dominant until the 1980s." {8080, in 1974, was NMOS.)
https://en.wikipedia.org/wiki/CMOS#History

There is a much re-printed (under different names) RCA paper 'CMOS Linear Applications'. The National re-brand of the RCA paper (is OK, RCA sold-off a lot of CMOS IP), National Semiconductor Application Note 88, says July 1973; I dunno if that date is RCA or National.
https://shrubbery.net/~heas/willem/PDF/NSC/AN/AN-88.pdf


Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on January 25, 2025, 07:06:06 AM
Hi
Yes about as I remember it and yes for developing a new type of semiconductor
you need a military application and then there are funds. Eventually you can release it
commercially. Yes back jn late 70's early 80's
the CD4XXX series was still where I live unprotected and raw transistors and compared to today this technology is now really old but it wasn't at the time.
The CD 4XXX you can buy today have diode contraptions to protect the internals and those make it so that you have to put a DC bias to make output rest at mid supply.
Elder engineers I know were back in the early 80's using CD4XXX Series for control systems while some refused and said TTL was faster.
Then some really old engineers used discrete gates to get higher fan out.
There was a professor at the Technical High School that would on the blackboard explain functions of various gates with discrete transistors something considered very old fashioned by the engineers in spe that are my age.
Engineers my age in those fields don't use CD4XXX Series anymore.

Back in the late 70's there was a lively discussion about using concrete in the subway system because building materials should be 100 years old to be considered stable.
As contrast Apple removed the headphone jack because the telejack is 100 years old

Have fun

Bjorn Juhl
BJF Electronics
Sweden

Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: PRR on January 25, 2025, 09:29:59 PM
My second job was maintaining a "computer controlled tape machine": a dozen RTL chips. IIRC, in little round cans, the design started before DIPs.
(https://i.postimg.cc/v1xCP9wJ/vin-Ad67-Crown-SX824.webp) (https://postimg.cc/v1xCP9wJ)

I can't put "RTL" on my résumé because they never failed (was always tarnished connectors) *and* because nobody today knows  what TTL is/was. It is 17th on Wikipedia's "RTL" page (https://en.wikipedia.org/wiki/RTL).

Donald E. Lancaster (1969). RTL cookbook
GE Transistor Manual (3rd–7th ed.). General Electric
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on January 26, 2025, 01:07:11 AM
Hi

Very Awesome!

Yes for sure young engineers of today here I have noticed at lectures hardly know the meaning of TTL and also surplus dealers I know
would buy Cdxxx series but not TTL , 74 series with the argument it is not possible to sell TTL anymore.
There was almost a Beatles versus Stones opposition among engineers about CMOS and TTL and it can be seen even in vintage music related circuits where some used TTL or CMOS for the same type of logic
It's all Ardinuo, Raspberry etc these days.
Back in the early 80s though some engineers I know said TTL was superior to CD4xxx in terms of speed, the switching frequencies that could be used and not as fragile. To me TTL was not interesting because there were no audio application but CD4xxx was interesting and not only for amplifier applications. However the only shall we say digital control system I ever built a selector of channels and functions in a rack I prototyped with CD4XXX series but fan out was too low as I needed to drive LEDs to indicate state and so the simplified version all discrete all BC557 and BC547 ended up at 74 transistors that was an interface between internal switching with CD4016s and HF11s and an external programmable and MIDI compatible  controller that could switch two state to ground such as changing channels on various guitar amplifiers. I actually really liked the idea of discrete gates and that allowed making custom gates and so cutting down the number of gates needed.
The handbook I had for that went out of print in the late 80s but it still an elaborate handbook on use and formulas of dimensioning discrete circuits that I consult to this day.


I recall making an amplifier out of CD4011 by converting a NAND gate to an inverter but it was back in the 80s and internal design might have been cruder not buffered nor protected

Here link to Don Lancaster RTL handbook and it is an interesting read today
https://www.tinaja.com/ebooks/rtlcb.pdf

Have fun
Bjorn Juhl
BJF Electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Rob Strand on January 26, 2025, 10:05:05 PM
Quote from: FiveseveN on January 13, 2025, 04:17:13 AMYour experiment is based on a false premise. We're talking about open loop gain here. x10 is not going to show you anything significant:

(https://i.postimg.cc/8c12hytq/cmosgain.png)

That plot comes from National Semiconductor application note AN88.   If you read the fine print it's actually a closed loop response, using a circuit with input and feedback resistors.  *However*, as much I could work out the feedback resistor is 10MEG and the input resistor 1k.  The resistor ratio is so high that the plot is essentially open loop gain.

Quote from: edvard on January 12, 2025, 10:49:55 PMn the end, my experiments with LTspice in regards to headroom clipping proved me mostly right, so I still say the clipping effects from reduced headroom are FAR more effective at producing distortion than any intrinsic gain induced from lowered supply voltage, but I'm still chasing noise floor nirvana.

MOSFET models are rarely accurate in spice.   I've got quite a few CMOS models some using simple LEVEL 1 models and other using more complicated models.   The finer characteristics of the LEVEL 1 models will never look like the more complicated models, however you can match specific characteristics for various supply voltages.

The interesting thing is most circuits and most models show an increasing open loop gain with *increasing* voltage.

To get the decreasing loop gain with increasing voltage seen in the plot you need to tune in the 'lambda' parameter in the MOSFET spice models.  Lambda is a channel modulation effect, more or less equivalent to the Early voltage on BJT's.

We know these devices have fairly low transconductance (gm) so in order to get the high gains in the plot the effective load resistance needs to be quite high.   That is part of the hint that lambda is important.   What else follows from that is AC or DC loads on the output will reduce the open loop gain.

It's one of those things where the devil is in the details both for the circuit and for the mosfet models.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: amptramp on January 27, 2025, 06:54:52 AM
A long time ago, I was working in a remote sensing department where we were taking tiny signals from individual detector diodes and amplifying them with transresistance amplifiers, like inverting op amps with no input resistor.  The gain of the circuit for incoming current was the feedback resistor which in our case was 25 megohms.  Holding the detector diodes to a fixed voltage gave the best linearity for the signal.

The op amps were expensive so we tried CMOS cooled to liquid nitrogen temperatures and run at 12 volts.  The input protection resistors contributed some noise and it was definitely not ideal but we characterized the performance running at -196°C which is one quarter of the absolute room temperature, so we would get half of the noise we would get at room temperature.

In the middle of the voltage range, each of the six inverters in the pack would pull up to 8 mA of current, so if the full package was biased to the midpoint, one inverter IC would pull 48 mA.  At irregular intervals, we would notice spikes in the output caused no doubt by running far below the minimum rated temperature.  We decided to not pursue any further development along this line but it was interesting to see CMOS operating in the linear region far outside of its ratings.

I don't generally trust CMOS amplifiers as being the best choice for amplifying linear signals but in some cases, they are good enough for rock and roll.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: edvard on January 28, 2025, 12:47:02 AM
Quote from: fryingpan on January 23, 2025, 06:48:01 AMAnyway, CMOS inverters are kinda noisy. They are quick and easy to use, as well as predictable, but they do come with a lot of drawbacks. IIRC, the upper threshold for voltage supply at linear operation is basically 9-10V, so headroom is what it is anyway.

You know, I have it on good authority that you can make an inverter from two complimentary MOSFETS, and as long as their specs are fairly close, they bias up just fine when wired for linear, which opens up the possibilities of high-voltage (e.g. up to the limit of your devices) inverter experimentation.  For example, 200v for a IRF640/IRF9640 pair, and 60v for a 2N7000/BS250 pair.  Next time I have a few pennies saved up, I'm gonna do it.  For science!

Also, I may be whackin' another hornet's nest here, but in my experience, most of the noise of CMOS inverter dirt circuits is due to the large value feedback resistor usually employed for maximum Rock & Roll.  I learned from another DIY'er here to try cascaded stages with smaller value resistor networks (1k-10k input, and 100k-220k feedback) and I must say the results were pleasing.  I can get serious metal tones from 3 stages of 10k/100k driven by an op-amp set for 5x with the "gain" backed off just to the point you hear the hiss drop, and even at full-tilt it's not bad.  And with carbon-comp resistors to boot.  Skwungey...
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on January 28, 2025, 01:47:30 AM
Hi there

Yes looking at the graph in the application note

And I think it looks just slightly different from the presentation specifically for CD4069
simply the CD4069
had sbout 1KHz open loop bandwidth at VDD 5V....however the chip in the application note
AN88 has considerably higher bsndwidth at 5V and about 1 KHz at VCC 3V
So all inverters are not created equal;)

So looking at AN88
Open Loop Gain and Open Loop Bandwidth
Vary with VCC/ VDD
At 5V you'd get 40dB Gain but at lower bandwidth than at VCC/VDD = 12V where you'd get 10dB less open loop gain

Due to the low open loop gain closed loop computation gets rather complicated
but an increase in open loop gain by 10dB under closed loop conditions would not be dramatic but rather be hard to detect.


But there are other considerations like output swing and performance under closed loop,closed loop frequency response, feedback factor , distortion or shall we say linearity? Even with distortion as goal linearity is a concern : if you look for making a linear amplifier to distort but that would return to linear operation when overload is removed that is a different thing than just creating gobs of distortion;)

Just typically you might get 20dB closed loop gain and ofcourse that gives only 10dB
to trade with if you have 30 dB open loop gain. One could ofcourse use three inverters inside a feedback loop and hope for low phaseshift and thereby dramatically increase open loop gain;)

But one must consider the dissipation for the capsule so making two amplifiers out all six in a hex inverter could lead to over heating of the chip

In the article on U66 it was pointed out that over heating was a consideration and why the were not using more than three inverters per hex inverter.

All this is to say that firstly open loop gain and bandwidth may not be the same for all possible inverters that could be used as linear amplifiers.

Secondly differences in raw open loop gain might be hard to detect or negligible.

But yes if you control supply voltage you should hear sound change with voltage
but the usable voltage range may vary with the device used

I recall tests I made with CD4069 and CD4049, CD4011, CD4007
useable VDD for either connected as inverter with feeeback was between 6V and 12V
very subjectively ofcourse and it was a long time ago as in the mid 80's
One out of 57 models I make uses a CD4xxx as amplifier it's a version of something I made in 1982 but today it needs extra bias resistors to make output rest at midsupply.

Good question how well LT spice semiconductors compare to real life semiconductors.

Have fun
Bjorn Juhl
BJF Electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Rob Strand on February 01, 2025, 05:19:51 PM
I'll  throw this up for you to think about:   
What is the actual cause of the HF roll-off in the Nat Semi gain plots?

- There's no load capacitance specified in the test configuration.
  It will cause some roll-off and at low voltages the gate output impedance
  increases.

- On the other hand some feedback capacitance could also cause roll-off.
  The higher gain at low voltage would make the Miller effect worse
  at low voltages.
  However, for this to have an effect in the test ckt we need some input resistance (R1).
  I've assumed 1k but if the test ckt was 50 ohm (straight from a signal generator) that
  would greatly affect the results.

FWIW: Spice would model the load capacitance to a large degree but spice doesn't model voltage dependence of the MOSFET capacitances which would confound and voltage dependency of the response cut-off.

In the past I've assumed a capacitive load.


 
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: amz-fx on February 02, 2025, 03:43:59 AM
The datasheet for one manufacturers 4007U chip has a chart that shows the change in Gfs as the voltage supply is increased:
(https://i.postimg.cc/7ZT3jPfb/cd4007.png)

regards, Jack
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on February 02, 2025, 08:03:14 AM
Hi there

OK random thoughts

Perhaps the first question to ask is what is the desired bandwidth?
Second question what are the properties of the source such as internal impedance, and peak to peak output?
Third question what are the properties of the load ?
Forth question what is the amplifier stage intended to do?

Frequency range can be controlled in amplifier stages via a number of means one being Miller capacitance.

Example in a tube amplifier the resulting sound and total gain depends on a number of ghost components so called be cause they are invisible but they define the desired behaviour within the desired bandwidth. Once you look at such a circuit at frequencies beyond human hearing the circuit looks different
Any circuit looks different when looked at high frequency: some components disappear more or less when you make a model and others that had very little significance become increasingly important with rising frequency. This is important when combating oscillation.
As per Murphys Law regarding amplifiers and oscillators
Amplifiers always oscillate , oscillators more seldomly

I don't have any first hand experience with spice but I have done many experiments in real life

Any amplifier study must include the source and the load.

Yes these inverters change properties with voltage. As for roll off in the AN 88 the inverter has a LP slope that begins at roughly 1KHz
The corner frequency is moved upwards with increasing voltage and so the voltage the inverter sees at its supply terminals will affect both gain and bandwidth.
Property change with CD4xxx series are obviously a little different

Oh yes capacitance in feedback will cause a roll of but the input but the computation of its effect is not as straightforward as with an OP amp because of low raw gain and input of inverter is not really a virtual ground.

With filtering or equalising to desired results who do you please your eyes or your ears?
The answer to which can be that it depends on the application

Absolutely higher gain open loop gain increases the Miller effect and really this is a good way of look at  the inverter that it is a more similar to a common source or emitter transistor stage than it is an OP amp and yes the effect of miller capacitance increases with source impedance as well

Someone who is handy with spice might alter the Mos Fet model to behave more like real world components.
The Mos Fets I have used have depending on the circuit been usable far beyond the human hearing, while I obviously been more interested in what they could be used for in the context of musical applications.

A load is always capacitive but a question is if this capacitance is important at the frequencies of operation. Most often the capacitances at load may be ignored at the operating frequency: if the bandwidth that we are interested in of the source is 20KHz then if response bends of at 200KHz  or at 440Khz is of less importance.

I think assuming a capacitive load is always a good thing ;)

Have fun
Bjorn Juhl
BJF Electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: PRR on February 02, 2025, 10:36:09 PM
Quote from: amz-fx on February 02, 2025, 03:43:59 AMchange in Gfs as the voltage supply

But the working Voltage Gain is Gfs times the output impedance. Gfs is pretty sure to rise with voltage/current. The rise at low voltage may be a rise of output impedance at low channel voltage. (And thus swamped with any normal load.)
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: amz-fx on February 03, 2025, 09:16:36 AM
Quote from: PRR on February 02, 2025, 10:36:09 PM(And thus swamped with any normal load.)

One of the design limitations that has to be taken into account when working with cmos linear amplifiers is that the load resistance on the output will reduce gain. Even a 1M scope probe will cut gain and a 100k volume pot will make a big difference.

In one of the other datasheets, for normal operation it is recommended that the feedback resistor be less than 1M and the series input R should be more than 3K. (74HC04 if I remember correctly)

regards, Jack
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: Rob Strand on February 04, 2025, 11:15:12 PM
Quote from: amz-fx on February 02, 2025, 03:43:59 AMThe datasheet for one manufacturers 4007U chip has a chart that shows the change in Gfs as the voltage supply is increased:
(https://i.postimg.cc/7ZT3jPfb/cd4007.png)

regards, Jack

As shown gfs is driving into an AC short which would remove any channel modulation effects (which cause the decreasing *voltage* gain).

If you look at the whole NXP datasheet you can see the current plots and the voltage gains don't match the National Semiconductor data.    Off hand the drain current vs output voltage characteristics were in national semiconductor AN77, and maybe some in Motorola/On-semi datasheets.

I think BJF was getting at some devices give different gains.   And here the the manufacturer's data don't agree.   If you look at old RCA/Fairchild datasheets you can compare CD4007 and CA3600's and even they don't match.   Coming up with spice models is a bit of a moving target.   Many spice models are way off the datasheets.   If you massage the models it's unlikely LEVEL 1 models will match over a wide range of supply voltages.
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on February 08, 2025, 04:16:48 AM
Hi there

Other thoughts just looking at the circuit topology and theoretically and from basic transistor technique theory

This type of stage would at a glance and with out voltage feedback have high input and medium output impedance and the available output current would be approximately a couple of millAmperes and it would not be linear but rest at either supply side depending on what is at the input and phase would be inverted, and amplification would be high from DC and frequency Zero but would start to fall at rising frequency due to Strat capacitance; but with voltage feedback the stage would be linear within a span before it overloads. With voltage feedback some excess open loop gain could be traded for more bandwidth and lower output impedance but there is not so much excess gain to be traded at audio frequencies.
Interestingly output impedance would be lower as per definition looking back into the output but current drive capability still limited at a few milli Amperes and also because  of the topology if load is lower than medium also open loop gain will fall so given the voltages load should preferably not be much lower than 10K unless losses are either acceptable or desired; voltage feedback as shown would lower input impedance but as before not so much higher drive capability
A way around that would be to make voltage feedback only for DC by splitting the feedback resistor in two and at the joint place a capacitor to ground and this can be made into a filter if desired but anyway this would greatly increase input impedance however the circuit may need a series resistance with input anyway or there likely will be instability and for connection to outside world it would be advisable to use a resistance at input partly to protect the input but also gain will reach maximum if input is grounded which can be a problem with standard electric guitars;)
Regarding maximum gain with voltage feedback for high frequencies defeated it could roughly be around 30dB.

So linearity  would greatly improve and losses minimised if the stage would be buffered and losses at output minimised.

Yes there are obviously great differences
and personally I have really only experience with the CD4xxx series also because that was a statement thing at the time

And really these are made for two state output and what happens in between is not important as long as there is a very distinct shift so that you don't end up the same way as like the early transistor computers built
in Sweden using consumer grade germanium transistors type AC127 which randomly due to leakage ended up at a stage of "maybe"
So the linear portion at border of ON and OFF is a mere consequence of making distinct ON and OFF state

In analogy with tube triodes also about datasheets there is a portion at the beginning if Grid graph where at very low Ugk and it's a blur simply because it is out of intended use but at this point and at very low Ua say 10-15V Ia is proportionate to Ig! and the triode becomes a current input voltage output device and is operated by the beginning current
That such a state exists is something that can be shown in experiments but it's not mentioned in tube literature as it is  far from the intended working points and the linear portion is small and not particularly useful unless you want to make use of worn down triodes at low voltage as mostly nonlinear amplifiers
( please excuse those of my tube expressions if not accurate in English because I learnt this in Swedish and German and I just translated them off the top of my head)

For making an accurate Spice model perhaps experiments and studies on
various inverter types could be done and result in not only more accurate but several
models meaning choose inverter from 74 series or from CD4xxx

Have fun
Bjorn Juhl
BJF Electronics
Sweden
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: blackcorvo on February 10, 2025, 02:16:38 PM
I believe the U66 amplifier mentioned before would be this one?

http://www.hififorum.nu/forum/topic.asp?TOPIC_ID=87203
Title: Re: CMOS Inverters: Lowering the voltage does not increase the gain
Post by: BJF on February 10, 2025, 07:34:26 PM
Quote from: blackcorvo on February 10, 2025, 02:16:38 PMI believe the U66 amplifier mentioned before would be this one?

http://www.hififorum.nu/forum/topic.asp?TOPIC_ID=87203

Hi,

A couple of posts down yes there is a part of it from Radio Television magazine 1978.
The preamplifier of this was also used for a guitar amp as I mentioned and if you plug guitar into phono input you get a hefty amount of gain and because there is no typical guitar amp filtering you get a smooth sound in a fashion that was popular among some at the time to place distortion between preamp and poweramp to mimic poweramp distortion and getting heavy gain by bypassing tone controls. Through Freestyle it sounded as I just described smooth and midrangy. and also yes a popular poweramp from Elketur of course

Thank you and have fun
Bjorn Juhl
BJF Electronics
Sweden