SO I've been tinkering around with the below schematic, and I went ahead and whipped it up, but it won't work. All I get is a faint muffled signal. My question is, can anyone see why it wouldn't?
I don't see a schematic.
whoops!
:icon_redface:
(http://i85.photobucket.com/albums/k42/goodoldpatrick/Untitled-1-2.gif)
The .1uF cap is isolating the first stage from the second stage, so no DC is passing along to assist in biasing. You'll have to be sure you're providing proper biasing for that second transistor. Looks like the bias is being pulled to ground to me. As a lazy test, I'd just short out the .1uF cap to see what happens when you flood that second transistor with some DC.
hmm, that didn't help either. after taking voltages for the first tranny, i'm getting over the volts on the emitter, and full supply on the collector. so i'm guessing i have something wrong around the bias of the first transistor. i also tried changing the 820k to a 100k to make an even voltage divider for the base of Q1, but that didn't help either.
i think i might have found the issue. my pcb layout i made looks like it might have the base of Q1 connected to the top end of the 820K instead of the divider. I'll check and let you know.
alright, i was wrong, layout checks out. I also tried removing the two resistors between the two stages and that didn't help either. I'm about to scrap this thing and start over...