DIYstompboxes.com

DIY Stompboxes => Building your own stompbox => Topic started by: Gus on September 17, 2011, 11:24:20 AM

Title: JFET gain stage DESIGN
Post by: Gus on September 17, 2011, 11:24:20 AM
I have a sim of how I would DESIGN a JFET gain stage for guitar.

I don't seem to get many posts in the threads that I post sims and graphs of circuits.  Is it people don't understand what I am trying to show?  

Is anyone interested in seeing how I would DESIGN a JFET guitar gain stage?  I posted hints about gain stages like this in the past and even posted the amp name you could find JFET gain stages like in the sim.

I think people would start to use this type stage once they understand it.  This sim uses a J201 because DIYer's SEEM to be stuck on using this JFET.  The J201 model used is from a post Of STM's
http://www.diystompboxes.com/smfforum/index.php?topic=71466.0
Title: Re: JFET gain stage DESIGN
Post by: Earthscum on September 17, 2011, 11:45:50 AM
Even though you don't get much reply to them, I don't think effort is wasted.

The Jfet sim, I would like to see. However, you may do a MPF102 as well, and see how much gain you can tweak out of it, then for fun combine the two in an optimal way to take advantage of the J201's higher gain, and the MPF102's higher current handling/output (low impedance driver).

Personally, I've been enjoying them. I actually have been referencing them when I'm screwing around my breadboard. The pics are nice visual aid, for sure.
Title: Re: JFET gain stage DESIGN
Post by: waltk on September 17, 2011, 12:08:19 PM
I like to see them also.  Remember there may be lots of people viewing them, who don't have anything usefull to add.  Also lots of others who are just in the habit of lurking, and never reply to anything.

For example, your "Simple buffer schematic" thread had 2 replies, but 611 views.  So please don't give up on sharing.

Title: Re: JFET gain stage DESIGN
Post by: Gus on September 17, 2011, 12:12:15 PM
(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=46220&g2_serialNumber=1)
(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=46221&g2_serialNumber=1)

R3 acts like a somewhat constant current device.  R3 sets the current in the circuit so you get a 4.5VDC drop across the 39K drain resistor.
R3 is what you adjust to bias the JFET used

The - supply with R3 is what is different than what I have seen for guitar JFET circuits in this and other forums

Note R2 is a gain control one can adjust this value without affecting the DC bias points.

JFETs in microphone can have up to 3gig gate to ground In this one you have a large range of gate to ground values you can use for R4.  R4 can be lower than 1meg

+ and - 9VDC supply, need the -9VDC for the QCC

You can find a circuit like this in the fender solid state Harvard amp schematic in one of the Groove Tube books.

This is a sim for +-9vdcc supplies and a J201.  If using higher voltages you may need to adjust some values and use different JFETS
Title: Re: JFET gain stage DESIGN
Post by: waltk on September 17, 2011, 12:12:47 PM
Thank you!
Title: Re: JFET gain stage DESIGN
Post by: Earthscum on September 17, 2011, 12:25:58 PM
I see it's biased as if it's running from a single 9V supply. Does this allow for a (positive in) negative swing well below the ground without clipping? It only allows for 4.5V upwards, correct?
Title: Re: JFET gain stage DESIGN
Post by: WGTP on September 17, 2011, 12:40:37 PM
Gus, your posts are usually over my head, but I enjoy looking at them and seeing how you do things.  The visual stuff really helps.  

I have 10 new J201's that I have been waiting for something to do with.  I have had more succcess with mosfets for some reason, but I'll try this one.  ;)   :icon_twisted:   :icon_rolleyes:   :icon_cool:
Title: Re: JFET gain stage DESIGN
Post by: caspercody on September 17, 2011, 01:31:42 PM
I also want to thank you for your work! It is over my head also, so I usually do not reply because I have no input. But I do breadboard and enjoy making the different stages.

Thanks
Rob
Title: Re: JFET gain stage DESIGN
Post by: deadastronaut on September 18, 2011, 03:50:24 AM
Quote from: WGTP on September 17, 2011, 12:40:37 PM
Gus, your posts are usually over my head, but I enjoy looking at them and seeing how you do things.  

me too,  :icon_redface:

example nooby question, what is that 2.5H...is is an inductor or something, just never seen it on typical layouts/schemo's..?

i'm messing around with fets at the mo, so this caught my eye... :)
Title: Re: JFET gain stage DESIGN
Post by: arma61 on September 18, 2011, 06:32:59 AM

^looks like all components before the word "input" are there to simulate guitar signal, pickup impedance, tone, cable capacitance ecc.. as stated on the schematic.

Ciao


Title: Re: JFET gain stage DESIGN
Post by: deadastronaut on September 18, 2011, 06:52:54 AM
oh ok.... :icon_redface:

cheers armando.. ;)
Title: Re: JFET gain stage DESIGN
Post by: Gus on September 18, 2011, 08:36:23 AM
L1, R6 a single coil pickup with 2.5 Henry inductance and 7k ohm resistance
R7 C3 tone control 250K at max treble and a .01uf cap
R8 250K volume control at max volume
C4 10 feet of 37pf a foot guitar cable

Select a Id drain current less than the JFETs IDSS at about 9VDC drain to source 4.5VDC / 39k = .115ma
.115ma x 82k= 9.46VDC this also means the source is a +.46VDC above ground
The current in R1 and R3 have to be the same(more correctly about the same the only other path is gate leakage and that is small)

9.46VD across the 82K acts somewhat like a constant current device to so even with different J201s the voltage drop will change but by how much

some made up numbers to show the way R3 sets the DC current of the circuit.  I have not measured J201s
9.0VDC/82K=.109ma      39k X .109ma=4.28VDC drop across R1  4.72VDC drain to ground
9.8VDC/82k=.119ma      39k X .119ma=4.44VDC drop across R1  4.56VDC drain to ground

OR one can use a constant current device instead of R3

Now to get gain from the stage you need to add C1 source to ground for max gain or C1 and R2 for less than max gain.
Being  JFET stage R4 can be larger 4.7meg and C5 lower value .001uf(1000pf)

Green trace is from the input node C5, R9
Blue trace is from the output node C2,R5
Title: Re: JFET gain stage DESIGN
Post by: Gus on September 26, 2011, 01:33:29 PM
Anyone build it? 

Do people understand how R3 and the - supply work to bias the circuit?

Title: Re: JFET gain stage DESIGN
Post by: slacker on September 26, 2011, 06:02:21 PM
I understand how the biasing works once you know that about 0.1ma of current causes about a 4.5 volt drop across the FET, what I don't understand is where these figures come from.
I had a look but I couldn't see it, is this relationship something you can get off the datasheet? Or do you set R3 by experimentation and once you've found the value for a particular FET it will work for others of the same type?

I'll try and build it if I get time.
Title: Re: JFET gain stage DESIGN
Post by: Quackzed on September 27, 2011, 01:29:54 AM
yeah, gus man, don't be disparaged! i for one have got a real kick out of your posts. thought as you are aware, your approach isn't as simple as 'use this circuit to get x sound'. rather you offer a truly in depth look at what is necesarry and what is extranious in a circuit.
i especially appreciate how your personal approach first identifies what matters in a guitars output. it stands repeating. you rarely overlook the output impedences of standard passive pickups and have gone to some lenghts to appropriately identify important aspects of their load in your designs. cable capacitance,  inductance, etc... imho what you focus on seems to be largely overlooked by many designers.
it isn't always comfortable for a quick fix mentality, however i feel your input places emphasis on whats coming IN and how to handle it with different active components... much appretiated man! i believe at the very least, you shine some light on what a guitars needs are and have some valuable insight in how to handle a guitar signal. anyone can set up an opamp clipper, but not everyone can see the effects of impedence or gain on bandwidth and frequency response, insightful and eye opening for sure. you have definately made me think twice about 'simple' circuits and their interaction with pickup loads and what you need to be aware of when designing gain stages.
really good stuff. not as 'flash' as some stuff, but in depth no b.s. analysis of a circuits 'real world' behavior. Cheers!  ;)

Title: Re: JFET gain stage DESIGN
Post by: brett on September 27, 2011, 09:05:46 PM
Hi Gus
definately don't get discouraged - you are a guru, and your ideas are solid and fresh.

A lot of people take time to understand or re-discover useful information. RG's classic "Technology of the Fuzz Face" is a treasure even though it is 10 years after it was written, as are your threads on the importance of the pickup in the tone of the Fuzz Face.

As for jfet stages. I really like them - they have high intrinsic input impedance (which is easily lowered) and are easily cascaded or mu-amped. IMO the stratoblaster is one of themost versatile and best-sounding boosters available. As for the J201 - it has a high Vgs(on/off), and Vgs is correlated with gain. Hence a J201 at -1V is more attaractive to people seeking lots of gain than an MPF102 at -6V. 

Thanks again for all your contributions Gus.
Title: Re: JFET gain stage DESIGN
Post by: DougH on September 28, 2011, 01:15:55 PM
Those pic links don't work on my phone. Hmmm...
Title: Re: JFET gain stage DESIGN
Post by: GFR on September 28, 2011, 02:38:46 PM
Gus,

Sometimes I don't reply because in a short post you're able to give so much to think about, I'll think and analyze and simulate, play with different scenarios and then when I start to understand a small snippet the thread is already old :)

I like this because I can learn much more than if the information was "in your face" Thanks!

At the moment I'm going through some simulations of piezo pres you have posted a while ago, lots of cool stuff.
Title: Re: JFET gain stage DESIGN
Post by: DougH on September 29, 2011, 08:26:26 AM
Gus, keep at it. Takes time on a forum for things to sink in. Still waters run deep.
Title: Re: JFET gain stage DESIGN
Post by: WGTP on September 29, 2011, 04:14:53 PM
Almost 750 views, folks just don't know what to say.  ;)
Title: Re: JFET gain stage DESIGN
Post by: PRR on September 30, 2011, 01:08:28 PM
> The - supply with R3 is what is different than what I have seen for guitar JFET circuits

Because we generally want to do it all with one supply, preferably 9V.

> R3 is what you adjust to bias the JFET used

The great advantage of this plan is that "ANY" (almost) JFET will work for-sure withOUT bias adjustment. The trade-off, of course, is that we generally want to do it all with one supply.
Title: Re: JFET gain stage DESIGN
Post by: slacker on September 30, 2011, 02:55:30 PM
Would this work with a virtual ground, same as we do with opamps, so you had a fake +4.5volts and -4.5 volts? Think I'll breadboard it and find out.
Title: Re: JFET gain stage DESIGN
Post by: lopsided on October 07, 2011, 12:58:32 PM
Quote from: slacker on September 30, 2011, 02:55:30 PM
Would this work with a virtual ground, same as we do with opamps, so you had a fake +4.5volts and -4.5 volts? Think I'll breadboard it and find out.

Hello Ian,

have you tried the idea with Vref or "fake ground"?
I was thinking about it myself, but couldn't really figure it out.

J.
Title: Re: JFET gain stage DESIGN
Post by: tca on October 08, 2011, 09:29:17 AM
Quote from: Gus on September 17, 2011, 11:24:20 AM
I have a sim of how I would DESIGN a JFET gain stage for guitar.

Hi Gus,
what can you say about the harmonic distortion content of the output voltage. The voltage V2 controls the exponent of the power law that relates the voltage Vin of the FET stage with the drain current ID (see this thread about almost the same topic: http://www.diystompboxes.com/smfforum/index.php?topic=93889.0 (http://www.diystompboxes.com/smfforum/index.php?topic=93889.0)). Is it mainly 2th harmonic or you can you get some other higher ones?

With V2 negative I suspect that you are stuck with second order power law between ID and Vin (typical FET) and thus 2th harmonic prevails.
Any comments?

Cheers.
Title: Re: JFET gain stage DESIGN
Post by: PRR on October 09, 2011, 12:15:38 AM
> I suspect that you are stuck with second order power law

No. Set Gus' R2 (actually R2||R3) to your optimum K value.

(http://i.imgur.com/EalbO.gif)

The other theories seem to set Id to about halfway between zero and Idss. Gus' plan sets a current typically far less than Idss. I'm not math-enough to know if K has a different optimum.
Title: Re: JFET gain stage DESIGN
Post by: tca on October 09, 2011, 04:39:25 AM
As I understand it, the value of k is determined, or determines, the working point of the FET. R2 is in series with a capacitor and thus does not contribute to the the value of the "equivalent source resistor". It controls the gain of the setup but varying the value of R2 you don't get another working point. k depends on the voltage bias and on the source resistor (or a positive voltage source at the source).
Title: Re: JFET gain stage DESIGN
Post by: amptramp on October 09, 2011, 06:09:44 PM
It would be interesting to replace R3 with an LM337 with a resistor from the output to the adjust terminal to form a current source.  If the source is sitting at about +1 volt in the existing design, the current is 0.122 mA and the resistor across the LM 337 can be about 10K.  The advantage?  You would be able to use less than 9 volts for the negative supply and the current would not vary with the negative supply voltage until it became very low.  You could use an ICL7660 and not have to worry about the voltage drop or the audio frequency getting on the output (although it may contaminate the input supply).
Title: Re: JFET gain stage DESIGN
Post by: Gus on October 10, 2011, 06:44:35 AM
I did post one can use a constant current device.  

I picked the J201 because there are many posts with people using this jfet.

I picked + and - 9VDC for a few reasons.  You can use two batteries to do a test build.  One might have a +- supply in a power amp.  A person might have or can build a +- 9VDC supply for their effect floor board.  If you want more stages to build a preamp why not +- if you might use an opamp or a small power amp?

39K was picked for two reasons, one Id less than IDSS at 4.5VDC across the 39k and can anyone guess the 2nd?

Look for the solid state fender Harvard amp schematic.
Title: Re: JFET gain stage DESIGN
Post by: slacker on October 10, 2011, 12:41:00 PM
Quote from: lopsided on October 07, 2011, 12:58:32 PM
have you tried the idea with Vref or "fake ground"?

I tried it, but I couldn't get it to work, this was only a quick test though. I could get it to bias up in about the right place, half way between the virtual ground and the positive supply, but the output was very quiet. This is possibly because, like I said earlier in the thread, I don't understand how the current is calculated or worked out, so I don't know if it needs changing for the different voltages.

Gus's circuit works as described though. I tried it with a bunch of J310s as they're the only Fets I've got, and they all biased up around 4.5 volts on the drain.
Title: Re: JFET gain stage DESIGN
Post by: PRR on October 10, 2011, 08:39:31 PM
> As I understand it, the value of k is determined, or determines, the working point of the FET.

You can bias and set gain with one resistor.

This usually needs tweaking for each JFET.

With Gus' plan, R3 sets the current and R2 sets the gain.

You set R3 for current lower than Idss but large enough to drive your load.

You may set R2 according to whatever criteria:

1) set R2 for desired gain (without regard for linearity)

2) set R2 for desired gain non-linearity (without regard for gain) between near-linear through 3/2-power to square-law.

The advantage of Gus' plan is that Id is _known_ at design-time, assuming V- is consideraby larger than Vto. This allows selection of drain resistor and specification of power consumption without knowing the exact JFET which will be used.

If your goal is #2, then it may be easier to just use the K-factor than to use Gus' separate Id and Gain trims.
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 04, 2016, 05:09:37 PM
Quote from: Gus on October 10, 2011, 06:44:35 AM
39K was picked for two reasons, one Id less than IDSS at 4.5VDC across the 39k and can anyone guess the 2nd?

Look for the solid state fender Harvard amp schematic.

Let's add for completeness of this nice thread:

I assume for mimicing the same source-impedance (as presented to the next stage) as the 'original tube-version' has:

100k plate resistor, in || with the ECC83 internal R of 62k5  --> 39k

Bye
Title: Re: JFET gain stage DESIGN
Post by: mojokorn on January 04, 2016, 10:55:34 PM
Tricky stuff.  Very cool!  I still have some more time to start at it, but after about 5 minutes, or more like 10 minutes - got a bit lost in techy calculation world, this is what I'm seeing (mostly focusing on the JFET bias and not the eq stuff before it)...

Negative bias at the Source creates a) 2x the (6 dB) voltage gain and b) another 9V of negative bias for more headroom on the input across Vgs.  C1 and C2 decouple the DC bias from the AC input.  Not sure about the K, need to think on that some more.

Feel free to correct me if I missed something.

Gus, thanks for the brain-teaser and the a new take (to me anyways) on a JFET ckt.
Title: Re: JFET gain stage DESIGN
Post by: J0K3RX on January 04, 2016, 11:54:35 PM
Great Scott!!! :o This is it!!  A bolt of lightning is going to strike the clock tower at precisely 10:04 pm, next Saturday night! If... If we could somehow... harness this lightning... channel it... into the flux capacitor... it just might work.

Title: Re: JFET gain stage DESIGN
Post by: PRR on January 05, 2016, 12:24:10 AM
> Negative bias at the Source

Not more gain. A *closely controlled* FET current instead of hit and miss compromises with uncontrolled V(gs).

This is old stuff.

It is shown in Nat Semi's App Note 32 of 1970. TI bought National and mercifully preserves a bad fax of the Note:

http://www.ti.com/lit/an/snoa620/snoa620.pdf

Edwin/Ed Oxner and pals published a complete taxonomy of JFET bias schemes and techniques.

Designing With Field-Effect Transistors
Siliconix, Ed Oxner
(http://ecx.images-amazon.com/images/I/51vefV5FgyL._SL500_SX330_BO1,204,203,200_.jpg)
http://www.amazon.com/Designing-Field-Effect-Transistors-Siliconix-Incorporated/dp/0070575371
(This is a revamp of an older work which is now rare/expensive.)

*ONE* of the so-many Malvino books has a drop-dead simple FET bias lesson.
Transistor Circuit Approximations, THIRD Edition, 1980, Malvino
http://www.amazon.com/Transistor-Circuit-Approximations-Albert-Malvino/dp/007039878X

Any of these is better than pulling a source resistor out of your pants and then bodging the drain resistor with no proportion to the load (just to find a not-jammed operating point).

And JFETs do not ever quite "sound like triodes" because they have no plate-grid internal feedback (amplification factor is far higher than in-circuit gain). There is a paper which tries to add this with a lot of added active circuitry. Bah. If you want tubes, get tubes. They have never been cheaper (on the hamburger+gasoline price index).
Title: Re: JFET gain stage DESIGN
Post by: mojokorn on January 05, 2016, 12:38:08 AM
Thanks for the book recommendation.  I just found and ordered one on Amazon (Prime none-the-less) should be here in a few days.  Also bookmarked the TI's app note.
Title: Re: JFET gain stage DESIGN
Post by: mojokorn on January 05, 2016, 01:01:18 AM
Quote from: PRR on January 05, 2016, 12:24:10 AM
This is old stuff.

So old it's new to me.
Title: Re: JFET gain stage DESIGN
Post by: mojokorn on January 05, 2016, 01:23:54 AM
Good ol' Malvino.  Still have this from my college days...

(http://ecx.images-amazon.com/images/I/51R8AqboEdL._SX410_BO1,204,203,200_.jpg)

link supplied by Amazon (easier than uploading a pic).
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 05, 2016, 09:05:59 AM
Nice to see this thread reviving!   :)


If Gus or anybody else reads this, just curious to learn  if my answer to the riddle from Gus was correct ? 

Quote from: clintrubber on January 04, 2016, 05:09:37 PM
Quote from: Gus on October 10, 2011, 06:44:35 AM
39K was picked for two reasons, one Id less than IDSS at 4.5VDC across the 39k and can anyone guess the 2nd?

Look for the solid state fender Harvard amp schematic.


Let's add for completeness of this nice thread:

I assume for mimicing the same source-impedance (as presented to the next stage) as the 'original tube-version' has:

100k plate resistor, in || with the ECC83 internal R of 62k5  --> 39k


Bye
Title: Re: JFET gain stage DESIGN
Post by: alfafalfa on January 05, 2016, 12:47:28 PM
About the type of fet used ;  a short while ago I read about someone using a fet j113 and he really liked it.
I haven't tried it myself yet ( I don't have any up to now) but I'm curious if anyone used any ?

Alf
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 05, 2016, 06:13:21 PM
Quote from: alfafalfa on January 05, 2016, 12:47:28 PM
About the type of fet used ;  a short while ago I read about someone using a fet j113 and he really liked it.

It'll all come down to specs  (unless a certain artist is using a certain type in a custom made device  8) )

I did a quick compilation of FETs

(http://i.imgur.com/CGErxX0.jpg)
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 05, 2016, 06:23:41 PM
Quote from: PRR on January 05, 2016, 12:24:10 AM
And JFETs do not ever quite "sound like triodes" because they have no plate-grid internal feedback (amplification factor is far higher than in-circuit gain).
Bah. If you want tubes, get tubes. They have never been cheaper (on the hamburger+gasoline price index).

I agree, going tube is often easier than go to great lengths to emulate them.

Yet there might be space constraints (or other requirements) & then it can be fun to try to come close - OR- make something, say a FET-based circuit, that sounds as 'nice' (...) as possible, while not necessarily emulating tubes.

I currently have an interest in/use for a circuit that doesn't use tubes, is compact and sounds 'better'/'more interesting' (...) than the opamp-stages it now uses. So want to see where substituting with FETs can bring that box.

Bye
Title: Re: JFET gain stage DESIGN
Post by: PRR on January 06, 2016, 12:51:13 AM
> a quick compilation

Thanks.

Gm needs more info, as it will vary with current. Often the spec-sheet cites Gm at the *maximum* current (near Idss, so that column is a guide, though Idss spread is very wide). In much audio we run the FET at much lower current, thus much lower effective Gm.

NF Noise (hiss) Figure should also be checked. This varies widely with source impedance, also with frequency, and operating current. "0.5dB typ" may be measured at insane source impedance and huge current. Few FETs will hiss bad in reasonable guitar-system applications.

I'd say Cin is a non-issue in face of 300pFd of guitar cable capacitance and frequent use of 470pFd input shunts to reduce radio reception in bad areas. In a gain-stage, drain-gate C times stage gain gives Miller Effect much higher than the touted Cin.
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 06, 2016, 05:32:46 AM
Quote from: PRR on January 06, 2016, 12:51:13 AM
> a quick compilation

Thanks.

Gm

NF

Cin

Hi Paul,

Yep, realizing that a quick comparison is just that, it sure needs a pile of conditions added to make comparing FET-types meaningful & accurate. 

Gm, Cin, NF: I had only time for pulling quick figures from the tables; for a more accurate comparison we sure need to look at the graphs & compare at identical (& like you say also at the more relevant) conditions.

Meant as a first rough-very-rough comparison when various JFET-types started to pop up in this thread.
The Harvard-circuit Gus mentioned uses the J231, for this thread he switched to the more common J201.

Likely a moot point, but as a brain-exercise for myself I'm interested in what the most suited FET would be for my intended supply rails (+/-12V).
The Harvard runs the J231 at +/-15V (if those zeners are indeed 15V) and Gus 'translated' to the J201 at +/-9V rails. I was triggered by a remark from Gus about FET-type related to rails, in another thread.


Cin: fully agree with the (non-)relevance of this for the first FET. Dunno yet how it would be for subsequent stages, but there its relevance might at least be secondary as well (those cheapskate or cramped-for-space types (guilty) prefer to emulate tube-preamps by replacing all triodes, so there'll be a few additional FET-stages.
See for instance also the Fender Harvard (early solid state, not the II) schematic that Gus has mentioned.

http://elektrotanya.com/fender_harvard_018023.pdf/download.html (http://elektrotanya.com/fender_harvard_018023.pdf/download.html)

NF: like you say, less relevant. Say comparable to Cin-reasoning: if, then only important for first stage, unless after severe tonestack-attenuation, then there a reasonable quiet FET desired as well.

Bye
Title: Re: JFET gain stage DESIGN
Post by: Gus on January 06, 2016, 06:04:30 AM
Quote from: clintrubber on January 04, 2016, 05:09:37 PM
Quote from: Gus on October 10, 2011, 06:44:35 AM
39K was picked for two reasons, one Id less than IDSS at 4.5VDC across the 39k and can anyone guess the 2nd?

Look for the solid state fender Harvard amp schematic.

Let's add for completeness of this nice thread:

I assume for mimicing the same source-impedance (as presented to the next stage) as the 'original tube-version' has:

100k plate resistor, in || with the ECC83 internal R of 62k5  --> 39k

Bye

Yes to sim the rp for a stock tone stack.
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 06, 2016, 08:21:01 AM
Quote from: Gus on January 06, 2016, 06:04:30 AM
Yes to sim the rp for a stock tone stack.

Thanks
Title: Re: JFET gain stage DESIGN
Post by: clintrubber on January 06, 2016, 08:24:51 AM
BTW/FWIW*, w.r.t. J201, from Teemu Kyttälä, Solid-State Guitar Amplifiers (online pdf), pg208:

"Note: One should avoid using JFETs with low IDS – especially in buffering circuits.
For example, J201 is a commonly used FET - probably because it was once used in
the famous "Till" guitar preamplifier and "FET Preamp Cable", both designed by
Donald Tillman. However, the gate cutoff voltage VGS (OFF) of a J201 is about the
lowest amongst all depletion mode JFETs and with moderate source resistor values
this device can't even handle input signals that are greater than few hundred
millivolts peak-to-peak. This FET is a horrible choice for buffers and basically for
common source circuits as well: In an equal circuit, a higher current FET, like J309,
can handle input voltages higher than 1 VPP and even offer slightly greater gain.
Although popular, J201 is really not that marvelous device. Note that Donald Tillman
originally substituted a higher current model with a J201 solely because of improved
noise performance. Let this be a lesson to you: Always base your component selection
principles on circuit theory – not to a fact that a particular component was used in
some famous circuit! It might have worked there – likely it will not work as well in
another application."



*: less relevant w.r.t. the original topic of this thread (added rail, larger rail-distance)
Title: Re: JFET gain stage DESIGN
Post by: PRR on January 07, 2016, 01:25:33 AM
> Always base your component selection principles on circuit theory

And understand that theory.

I see what Teemuk is saying and it is quite correct as far as it goes.

But then how can we ever use a BPJ transistor? What Vgs(off) really is, is the distance from full-on to full-off. In a BPJ this is typically 60mV! (Take 10V and 10K, bias the base voltage so that collector is almost zero. Now reduce base bias voltage by 60mV. Current goes down by 10X, collector will come up to 9V out of 10V.)

Another nitpick: Teemuk's correlation of "high current" and "high Vgs(off)" IS true for FETs of the same geometry, it is not true for FETs of different geometry. Consider ten matched J201s in parallel: the total Idss is 10X higher, but the Vgs(off) stays the same (neglecting the practical specification-point that Vgs(off) is typically measured not at dead-zero but at perhaps 10nA, which is 1nA each in our 10X array, which will need a wee bit more Vgs to go "off"). Current is largely about area, Vgs(off) is largely about depth of processing.
Title: Re: JFET gain stage DESIGN
Post by: PRR on January 07, 2016, 02:05:21 AM
> what the most suited FET would be for my intended supply.....

Not 9V.

We ground the gate. The source has to be part-of Vgs(off) above gate/ground. The drain has to be most-of Vgs(off) above the source. Vgs(off) can be found from 0.2V to 8V, and you can't buy a narrow selection (maybe SmallBear, if you pay his staff). Taking part-of Vgs(off) as sometimes 3V, Drain has to be over 6V *minimum*, which is most of the 9V supply gone. Then we probably need to idle at 7.5V, the middle between 6V min and 9V max. That leaves little for output. Also quite a low value for source resistor. While we 9V folk lean to Vgs(off) far less than 8V, we sometimes have to take what we get.

> +/-12V ...  +/-15V

Between 24V and 30V, there's no great difference. Both are so much more than the hardly-ample 9V that either can work fine.

To over-simplify: Fender biased two of those stages with Gate "at" ground, allowing a huge 15V in source stabilization resistance. IIRC, 330K. Drain loaded in 150K. Source and drain currents are equal. If drop is 15V in 330K, it will be 7.5V in 150K. Drain is *sure* to be very-very near half of the zero to +15V range. Actually Fender biased a little lower, but the net result is most of 15V swing peak-peak, 5V RMS out.

Another point: JFET voltage gain goes up when designed for higher supply voltage, and goes down as about the square-root of current. Practical limit is the 30V-40V G-D breakdown voltage. However you could run +/-30V with gate near ground and most of the -30V only appearing in a source stabilization resistor.

Now that you have very exact control of current you can aim-down from 1mA to 100ua or 10uA, get 3X or 10X the voltage gain. The limit comes when you can not drive the load. If you steal tube-amp values, 200K is an upper limit (while you can use 1Meg resistors, stray capacitance tends toward 200K at the top of the audio band, unless you hammer at it).

The drain resistor should be 2X (to 5X) times lower than 200K, say 100K or 40K. Dart at the resistor rack selects 47K. With +30V supply and op-point around +15V D-S (and 15V across 47K), current should be 0.3mA. J201 Gm at 0.3mA is (how interesting!) 1.5mMho (1,500uMho, a familiar number). 1/Gm is 667 Ohms. gOs at 0.3mA is around 5uMho, or 'plate resistance' is 200K. Taking 47K 200K and 200K, 32K total, voltage gain is 48(!!). Taking maximum output as 30V/2.828= 10Vrms, gain of 48, maximum input is 0.2Vrms (stupid low-volt devices!). But we can raise that 0.2V to 0.5V by making effective 1/Gm 2.5X higher, which means adding 1.66K in series with the source's AC path (1.7K in parallel with an assumed 100K from source to -30V). Voltage gain is 19, 10Vrms out implies 0.5Vrms max input, which covers most guitar and hotter axes can use hi/lo jack input.

Note that in Fender's plan, V+ and V- do different things. The plus sets the maximum output, which maybe wants to be large. As noted, this could be +30V without harm. The minus is *only* to over-whelm the un-certainty of Vgs(off). For J201 we have spread of 0.3V-1.5V, a 1.2V uncertainty. -12V would reduce variation to 10% (+/-5%) which is plenty good for an audio amp (we mostly want to stay away from both rails, not hit an exact op-point). Even +35V/-10V would be a fine design. However doubling the voltage may quadruple the power demand, while not even giving twice the headroom, so may be diminishing returns. And the ways of getting both-ways supplies often favor about the same on both sides. So rounding-off from +40V/-10V to +/-15V or +/-12V sacrifices little and may be more practical.
(35)
Title: Re: JFET gain stage DESIGN
Post by: Gus on January 07, 2016, 05:46:54 AM
An older thread http://www.diystompboxes.com/smfforum/index.php?topic=103492.20 (http://www.diystompboxes.com/smfforum/index.php?topic=103492.20)
I used 201s because people seem to build with them.  I would use a different jfet in a build.  Based on textbook app note circuits
Look for the difference from the first post and gritz's posts at the end