Hello,

I have designed a hybrid chorus pedal, which has a complete analog sound treatment but I am digitally generating the two clocks signals for the BBD (MN3207). The BBD has two noise sources: clock noise and white noise. I have managed to filter out the clock noise however I am unable to get rid of the white noise ("hiss"). I have tried different filters and no luck....

I was thinking about using a compander (NE 571 or v571), however there might be another solution. Any ideas?

Thanks!

Simply you can't avoid hiss with BBDs...
it's a part of the sound (BTW why design it analog?).
This because hiss comes from the approximated signal reconstruction due to sampling...

You may add a compander, pre-emphasys and de-enphasys too, but you'll always get hiss on output.
You might find a reasonable compromise though...

The traditional strategies for minimizing noise, including those you listed, are:

a) companding
b) lowpass filtering, before and after the BBD
c) carefully balancing the two outputs of the BBD
d) clocking the BBD as high/fast as feasible
e) running as hot an input as possible
f) gating of the we path

Companding allows for use of 'e', and 'd' allows for 'b' to be as merciful as possible.  'C' addresses clock noise systematic and predictable), rather than hiss (random and unpredictable).

The Boss CE-1 and A/DA flanger both employ 'f'.  There may be others that use it as well, but I'm unfamiliar with them.

Overarching all of this, of course, is always layout.

A few more things that can make a difference are:

g) Careful setting of the BBD's input bias point. Poor biasing makes the noise figures worse.
h) A little "deadband" between the two clocks (tiny period when neither clock is high) can help.
i) Degraded clock edges. You need a clean switch-over from one to the other.

None of these are as critical as Mark's list of the major stuff, but BBDs are one of those things where you need *all* the marginal gains you can get if you're to get a decent result overall!

This might be the place to suggest an innovation: use a camera chip and clock the output from that with the input being from a LED driven by the audio signal.

Different clock rates give you different delays and the fact that the input is optical can avoid some of the input bias and headroom issues.  People are discarding cameras everywhere.  I see old 2 megapixel cameras and VGA cameras everywhere at garage sales and they generally go for low bucks.  You have to create an optical mask to keep everything on one pixel at the input but that could be done.  Then you use the clock signals as normal but you vary the frequency for variable delay.

Quote from: ElectricDruid on July 29, 2019, 03:43:11 PM
A few more things that can make a difference are:

g) Careful setting of the BBD's input bias point. Poor biasing makes the noise figures worse.
h) A little "deadband" between the two clocks (tiny period when neither clock is high) can help.
i) Degraded clock edges. You need a clean switch-over from one to the other.

None of these are as critical as Mark's list of the major stuff, but BBDs are one of those things where you need *all* the marginal gains you can get if you're to get a decent result overall!

Damn straight!

I often recommend to people setting up BBD-based circuits by ear to rule out as many "external audible interferences" as possible.  So, kill the dry signal by lifting one end of a connecting component, and listen with headphones, so no other sounds are contaminating what you hear.

QuoteThis might be the place to suggest an innovation: use a camera chip and clock the output from that with the input being from a LED driven by the audio signal.

Cool idea.

Makes me wonder what a picture of my butt would sound like  .

Quote from: Rob Strand on July 29, 2019, 07:56:38 PM

QuoteThis might be the place to suggest an innovation: use a camera chip and clock the output from that with the input being from a LED driven by the audio signal.

Cool idea.

Makes me wonder what a picture of my butt would sound like  .

Like crap 

J) Use two BBD's in a parallel, differential etc. set up.

Reticon SAD1024 datasheet shows most of the ways to get the best out a BBD and most can be applied to the MN types.

I've never played with a multitap BBD which seem to only ever have single-phase outputs. Presumably, you have to work a bit harder to get those clean? Or do they also cancel the clock somewhat if the outputs are mixed down equally?

Quoteh) A little "deadband" between the two clocks (tiny period when neither clock is high) can help.

When using the MN clock ICs, do the resistor-capacitor configurations make a difference? Some schematics show a resistor in series with the clock cap, while sometimes the cap is alone. Is it possible to obtain this deadband playing with these configurations?

Quote from: thomasha on July 30, 2019, 01:41:38 PM

Quoteh) A little "deadband" between the two clocks (tiny period when neither clock is high) can help.

When using the MN clock ICs, do the resistor-capacitor configurations make a difference? Some schematics show a resistor in series with the clock cap, while sometimes the cap is alone. Is it possible to obtain this deadband playing with these configurations?

My understanding was that the MN-series clock chips included the deadband and that that was one of the few advantages they really provide over rolling your own. I've never checked it on the oscilloscope though. The MN3102 datasheet only shows a mysterious "waveforming" stage after the "divide by 2" stage, so they're not saying.

Quote from: anotherjim on July 30, 2019, 08:30:02 AM
I've never played with a multitap BBD which seem to only ever have single-phase outputs. Presumably, you have to work a bit harder to get those clean? Or do they also cancel the clock somewhat if the outputs are mixed down equally?

That's a very interesting question.  Datasheets don't seem to be detailed enough to explain, but I never hear folks who own devices using the MN3011 0r 3214 complaining about noise, just about what a lousy job they do mimicking reverb.  I'm guessing that they combine the complementary outputs at each tap internally.  They would have to, or else the chip would need a lot more pins.

QuoteMy understanding was that the MN-series clock chips included the deadband and that that was one of the few advantages they really provide over rolling your own. I've never checked it on the oscilloscope though. The MN3102 datasheet only shows a mysterious "waveforming" stage after the "divide by 2" stage, so they're not saying.

Very interesting and it makes a lot of sense too.

If you look at delay chip datasheets (I just randomly pulled up MN3009) they clearly show the bi-phase clocks overlapping at the top of the waveform; ie. not crossing at 50%.  In fact there is a "Vx" spec.

That should ensure clean & distinct transfers between the buckets otherwise you get a "blurred"  bucket.

[EDIT: I need to look at the details again.  The MN3009 is P-channel whereas the MN32xx and MN33xx's are N-channel, which flip the waveforms as you would expect.]

QuoteDatasheets don't seem to be detailed enough to explain, but I never hear folks who own devices using the MN3011 0r 3214 complaining about noise,

Clock leak and general noise are different things.  If your anti-aliasing filter is actually filtering then it should be able to re-construct the signal.  However, if you only have half-pulses coming out then the level will be reduced to half. (It's a while since I've looked at the details.)

1) The datasheet for the 3209 shows the reverse "overlap".  I gather that, since the movement of the sampled voltage entails charging up the next storage cap in line, that is going to take some fixed time period, and the "deadband" allows for that requisite time to pass.

2) The clock pulses illustrated assume that no obstacle to the crispness of those clock pulses has been encountered.  In other words, the clock pin input capacitance has had no slew-limiting impact on the clock pulses arriving from the 3101/3102.  Remember that Panasonic provides upper limits on the clocking of the BBDs i the datasheets, predicated on the interaction between their clock-generator/driver chips and the input capacitance of the BBD clock pins.

Quote from: Mark Hammer on July 31, 2019, 09:40:43 AM
1) The datasheet for the 3209 shows the reverse "overlap".  I gather that, since the movement of the sampled voltage entails charging up the next storage cap in line, that is going to take some fixed time period, and the "deadband" allows for that requisite time to pass.

I thought it was the reverse - that the storage caps charge while the clocks are high. The deadband is then to make sure that there's no time when both sets of switches are on (which would leak charge from one cell to another). Instead, the deadband ensures one switch is fully off before the other starts to switch on.

Quote
2) The clock pulses illustrated assume that no obstacle to the crispness of those clock pulses has been encountered.  In other words, the clock pin input capacitance has had no slew-limiting impact on the clock pulses arriving from the 3101/3102.  Remember that Panasonic provides upper limits on the clocking of the BBDs in the datasheets, predicated on the interaction between their clock-generator/driver chips and the input capacitance of the BBD clock pins.

No, absolutely. Sharp edges are a must.

I have to say the PIC's NCO module is pretty much ideal as BBD clock generator. You can adjust the dead-end period in terms of "X counts of the system clock" (So 8MHz or 32MHz or something = sub-usec resolution) and you can generate frequencies up to 500KHz with ease. Plus the outputs can drive a 20mA load, so there's enough "oomph" to push the clock pin capacitance of quite a few BBD stages. The only problem is dealing with modulation, since a NCO only has discrete frequency steps.

<edit: dumb autocorrect>

Quote from: ElectricDruid on July 31, 2019, 10:30:11 AM
I thought it was the reverse - that the storage caps charge while the clocks are high. The deadband is then to make sure that there's no time when both sets of switches are on (which would leak charge from one cell to another). Instead, the deadband ensures one switch is fully off before the other starts to switch on.

Now that I think of it, yeah, you're probably right.  After all, something has to be applied to the gates of those itty-bitty FETs to allow the charge from the previous stage to pass onto the cap in the next one.  It's the "on" part of the duty cycle that results in charge-transfer.

QuoteI thought it was the reverse - that the storage caps charge while the clocks are high

Yes.  There's two types of BBDs:  NMOS and PMOS.   It's often written somewhere in the datasheet. All the signals get flipped (including Vb).  Also, there might some advantage in crossing the clocks while the clock voltages are within the Vdd to Vb band.  I suspect there's some subtle behaviour with those "tetrode connected"  Mosfets.

Quote from: Mark Hammer on July 29, 2019, 08:32:54 AMThe traditional strategies for minimizing noise, including those you listed, are:

a) companding
b) lowpass filtering, before and after the BBD
c) carefully balancing the two outputs of the BBD
d) clocking the BBD as high/fast as feasible
e) running as hot an input as possible
f) gating of the we path

Companding allows for use of 'e', and 'd' allows for 'b' to be as merciful as possible.  'C' addresses clock noise systematic and predictable), rather than hiss (random and unpredictable).

The Boss CE-1 and A/DA flanger both employ 'f'.  There may be others that use it as well, but I'm unfamiliar with them.

Overarching all of this, of course, is always layout.

Sorry to resurrect an old thread, but I thought I could add some newer information.

Based on lab results in collaboration with a friend, you can add these tips:
(g) Load the output with a current source instead of a resistor.  This increases the S/(N+D) ratio by about 12dB.
(h) Put a sample/hold after the output; gate it to sample during the middle 50% of each clock pulse; this eliminates the huge clock spikes inherent to a BBD output.
(i) Carefully design pre-emphasis and de-emphasis to cancel out accurately; choose a fairly low knee frequency (~500Hz).
(j) Use a MAX296 on the input, and another on the output, for anti-aliasing and reconstruction filtering.  Clock it at 16x the BBD rate.  You will still need a mild reconstruction filter (fixed, high corner frequency) at the MX196 output; this can be integrated with the de-emphasis filter.

Taken together, these will eliminate the need for companding and its ugly artifacts.  At high clock rates, the signal is so clean it's almost digital in quality.  Your filters will automatically track the clock rate, so you get a full range from long/dark/noisy to short/bright/clean delays.

"Load the output with a current source instead of a resistor"

That rings a bell or two, a long time ago I was given a circuit by a tech at Philips for a delay using a quantity of TDA1022 BBDs. To jog a memory somewhere, the circuit was cleaned up - was it by you Mark?

I'll try to find it.

Wasn't me.  I'm not smart enough for that.

I haven't looked inside one, but the Chase Bliss Thermae seems to have a digitally-controlled clock driving the BBD.  That's what allows it to do the melodic "interval jumping" it is capable of.  I'll have to ask Joel about it.