Hi guys,

Very new to this forum so please forgive me if I unknowingly break a few rules.

I've been trying to understand the BOSS DS-1 circuit (dual op-amp version) using a few sources, mainly including https://www.electrosmash.com/boss-ds1-analysis

I'm currently looking into the common emitter amplifier stage (the transistor boost before the op-amp stage) and haven't been able to find anywhere that has any solid answers to my questions. I did an electrical engineering degree so I like to dig deep into how everything works. My questions are, using the component names from the schematic in the electrosmash link:

-If the only thing that C2 and R4 are used for is to create a high-pass filter, then why is R4 connected to +4.5V and not ground? I know that this biases the signal up to a virtual ground of 4.5V, but this is then mostly removed by the second high-pass filter of C3 and R5 so I don't particularly see the use.

-Linked to the previous question, with that bias mostly being removed, how is the base of the BJT Q2 biased enough to not over asymetrically clip the signal on the negative side, let alone turn the transitor on? I've had a play around with some simulation of the circuit and I'm guessing BOSS left it that way to get some nice asymetric clipping as I can see from the simulations, but I don't understand how the negative side isn't completely cut-off due to there being no bias.

If anyone has some answers to these questions or a webpage with some good in depth explanations I would be super grateful!

Cheers,

Matt

Welcome, Matt!  (Sorry, that sounds wrong...  )

I took the liberty of moving your thread somewhere with more footfall.

Welcome, Matt    

The way I was taught is that the bias supply, being well-filtered, is somewhat isolated from the 'regular' active device power. So, sending audio signals to Vref this way is 'cleaner', less susceptible to noise on the ground plane.  It's "AC ground", where 'regular ground' is often a mix (can be noisy).  Note that all that is in the way of that return is the 47u cap to ground, assuring that only AC passes.  The other signal points that ground here will also find that cap to be a good isolation from crap on the power rail.  We see this a lot, notably in Tube Screamer-type circuits.  AC doesn't mind.

R7/R5 provide bias to Q2...

Quote from: GibsonGM on Yesterday at 09:23:07 AMR7/R5 provide bias to Q2...

Just to add that R5 is there to stabilize Q2 Base voltage..
In theory, Q2 could work just as well as without R5..

@eeyml8: IMHO (without any overweenig) DS-1 is a terrible design..

Quote from: eeyml8 on Yesterday at 07:17:55 AMIf the only thing that C2 and R4 are used for is to create a high-pass filter,

What is that cut-off frequency? Is it even audible?

Quote from: antonis on Yesterday at 01:40:34 PMIMHO (without any overweenig) DS-1 is a terrible design..

The second version (the one we're discussing, since it's the one in the Electrosmash article) where they swapped a single DIL amp chip for a dual DIP op-amp is particularly odd, since they made minimal changes but included both op-amps in the circuit, meaning one op-amp does basically nothing, while there are two transistor stages in front of it. It could easily have replaced one (or maybe both) of those to save a few parts.

Quote from: PRR on Yesterday at 02:16:10 PMWhat is that cut-off frequency? Is it even audible?

I haven't checked, but "3.3Hz" according to Electrosmash. So no, totally way below any audible effect. Those parts could get thrown away without losing anything. Go straight into C3/47n.

I'm not sure I'd go quite as far as Antonis' "terrible" but I'd certainly say "very odd". It's like Boss were only just getting warmed up!

 

https://postimg.cc/bGLyDvYM

Quote from: eeyml8 on Yesterday at 07:17:55 AMHi guys,

- If the only thing that C2 and R4 are used for is to create a high-pass filter, then why is R4 connected to +4.5V and not ground? I know that this biases the signal up to a virtual ground of 4.5V, but this is then mostly removed by the second high-pass filter of C3 and R5 so I don't particularly see the use.

Look at the original schematic m4268588 posted.  The 470nF and 100k are part of the JFET switching/dry signal.  From that perspective they are in the circuit.  The JFET needs to 4.5V bias.  The 470nF cap will be in series with the 47nF and affect the overall capacitance.

Quote-Linked to the previous question, with that bias mostly being removed, how is the base of the BJT Q2 biased enough to not over asymetrically clip the signal on the negative side, let alone turn the transitor on? I've had a play around with some simulation of the circuit and I'm guessing BOSS left it that way to get some nice asymetric clipping as I can see from the simulations, but I don't understand how the negative side isn't completely cut-off due to there being no bias.

I have a feeling it's not a big deal since the input cap is only 47nF.

---

Here's an analysis with some of the fine detail thrown in.  It agrees with spice.

Analysis of DS-1 gain stage.

Main thing to notice is the high voltage gain of the transistor stage will have
a strong Miller effect on the input impedance.  Once that kicks in the analysis is
complicated by loading effects at the base.

Bias to 4.5V
IC = (9-4.5)/10k = 450uA

Open loop gain:
re = Vt / IC = 58 ohm
RE + re = 22 + 58 = 80 ohm

Voltage gain from base to collector,
gain A = 10k / 80 = 125

Rin's are looking into the base node.

Miller Effect on 470k, (simplified without the 1)
Rin1 = 470k /  125 = 3.8k

Miller Effect on 250p,
Cin1 = 125 * 250pF = 31nF

Reflection of RE+re impedance to base,
assuming hFE = 300

Rin2 = 80*300 = 24k

Clearly, at the base the impedance is dominated by
feedback components.  To summarize,

Rinb = 3.8k // 24k // 100k = 3.2k
Cinb = Cin1 = 31nF

The 470n and 47n input caps are roughly in series
Cin = 1/(1/470n + 1/47n) = 43nF

The 43nF and 31nF form a capacitive voltage divider,
division ratio (1/31) / (1/43 + 1/31) = 0.58.

The overall voltage gain will then be 0.58 * 125 = 72.5 (37dB)

The effective capacitance of the high pass filter at the
input is the Thevenin impedance of the 43nF and 31nF,
which is the two caps in parallel:
Ct = 43nF + 31nF = 74nF

The resistance for the input high pass filter is Rinb = 3.2k.

So the input high pass cut-off is  f3 = 1/(2*pi*3.2k*74nF) = 672Hz.

In spice I got a gain of 37dB and a cut-off 660Hz, which is pretty close,
better than I expected from the basic analysis.   That's with the JFET switch
removed and no load on the output of the transistor stage.  ie. same conditions
as the above analysis.

(You might notice 670Hz is very much in the order of the 720Hz on the TS-9!)

So, R4 (as well as R19) is just a residual of original JFET bypass configuration..
(no comment..)

edit: Rob is by far faster..