YAJBQ (Yet another Jfet Bias Question)

[Dylfish]

Hi Guys,

I've got a few question and if there are any consideration's I've missed please correct me. I've read about the technical side of JFETs but i haven't seen any real guides of what is the best way to design from the ground up.

This is my assumption in basic terms for a self biased JFET.

1) Choose IDq and Vdq.

• Idq is within the IDss of the transistor is. essentially Idss/2 should be ok.
• Vdq is where the output is, so it should be half the supply voltage, giving the maximum swing possible

2) Choose Rg as Input impedance eg 1Mohm

3) Choose Rd using Ohms Law so Vd = Vcc/2 Approx

4) Pick Rs using Ohms law so (assuming Idq = Isq) Id should sit at a specific level/bias depending on Vgs.

What else is there to take into consideration or is this completely incorrect?

Also is it worth using a Spice/Sim product when using FET's or is simulation too inaccurate/Picky?

Edit: Also (on the sim) there seems to be quite a Vdrop over the JFET. VD = 7v  VS = .5v , If this is from a 9v supply, wheres the rest going?

Cheers!

[PRR]

Rd should be 2X to 5X the audio load impedance.

Minimum required Idss follows from there.

If you want gain, Vgs(off) should be small.

Typical Vgs(off) range on JFETs is a "not small" fraction of 9V, so 9V design is always marginal.

Rd is not simple "Ohms Law" unless you account for the Square Law curvature of a FET.

> quite a Vdrop over the JFET. VD = 7v  VS = .5v , If this is from a 9v supply, wheres the rest going?

Jackson? (There was a song.). The simulator knows where all the voltages are. If it isn't clear to you, you better post some pictures. However it *seems* you have not-enough current in your Rd to pull-down to a likely 5V Vd point. Maybe Rd is too small. Maybe Rs is too large. Maybe the JFET is too small.

[duck_arse]

dylf, here is 2 links, one to mosfets, but good anyway.

http://www.geofex.com/Article_Folders/mosboost/mosboost.htm
http://www.rason.org/Projects/jfetamp/jfetamp.htm

I have a load of application notes from Temic/Siliconix, starting from "AN101", has everything most you need to know about jfets. you'll have to search though, both companies were swallowed by ...... someone, vishay?

[Gus]

Vishay had the good app notes posted  AN101 etc.

[Dylfish]

Thanks Guys,

I've read alot of people saying that the best place to bias VD is around 4.5v, but wouldn't you rather it be a bit higher to the signal stays in the saturated region and doesn't stray into the ohmic region?

My thought for optimal swing range would be something like (Vcc - VP)/2.

Is my train of thought correct?

[smallbearelec]

Here is how I cobbled a two-stage preamp:

https://www.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm

Give me a few weeks and I will have tested devices available. Or you can sort your own.

SD

[PRR]

> something like (Vcc - VP)/2.

Yes.

However for good gain we want to pick a device with low Vp. (But NOT so low that input signal exceeds 2*Vp + toleances.) So "in general" the Vp correction to Vcc/2 should be "small". And the exact bias point is not critical. I would almost say "1/3rd to 2/3rd" rather than "exact 1/2". Generally if the 1/3rd or 2/3rd biases don't give enough headroom, an exact-1/2 won't be ample either (2.4dB difference).

[Dylfish]

Thanks guys.

From reading that link i realise how crazy the spread is with Jfets is unit to unit. When designing a repeatable design is it best to get the general part layout done (pcb or otherwise) then measure each FET and then bias accordingly by changing resistor values to match?

Is using a trimmer on Drain & Source advisable to dial in specific Vgs and Vd values depending on the specs of the FET being used?

Also on the smallbear article the circut is being tested with a generated signal of 10mv. I was to believe that on a humbucker that a somewhat aggressive pluck of the string can generate a voltage of upwards of a Volt. If designing a clean boost and simulating for minimal clipping, what value should I be using since there is a large difference (especially once amplified) between the 2.

thanks!

[PRR]

> upwards of a Volt

If it is that big, why are you amplifying?

Nothing in audio needs much more than a Volt until we get to the Final stage (loudspeaker output).

You need to consider gain dynamics. Yes you may have a Volt (i'd say half-Volt but maybe I'm weak). But essentially every guitar amp made, Full Up, will overload with 20mV input. To also take 500mV, cleanly, there needs to be a Gain/Volume knob *before* anything overloads.

If we assume 0.5V(rms) in and 2.5V out (7V p-p), you can't take a gain more than 14 in the first stage. If you twang a whole Volt, 7.5 is the max gain before a volume knob.

> designing a repeatable design is it best to ... measure each FET

Banjo World gives you a contract for One Million "Dylfish Boosters" at $30/each and delivered Friday. You can NOT sit there measuring FETs and trimming tweakers by the million; the time and cost will kill you.

Yes, ONE pedal DIY style the trimming is acceptable.

If you need to slap and ship without trim, you need to move to total bias voltage (FET and source resistor drop) much higher than the spread of Vto; so a supply voltage much-much higher than the spread of Vto. This usually means 24V supply. Indeed the early Yamaha Electric Grand used a chain of JFETs run on 24V (no trims).

[Thecomedian]

http://www.youtube.com/watch?v=tDQ0aBdUAHE


this video might help you with biasing and choosing voltages. FETs aren't linear for amplification unless it's fractional changes. I believe they're mostly used for current boosting as "buffer".