Negative Feedback / Source Degeneration

[Dylfish]

Hey Guys,

It's me with some more questions that may be me thinking too hard about the subject, but alas I shall ask them anyway.   

Today's Topic: Negative Feedback / Source Degeneration.

I have looked around and tried to find any maths or references other than "the negative feedback reduces the signal on the input" to try further understand whats happening.

When we use source degeneration, it allows a larger input that usual to pass without clipping. As far as I am aware this is due to the positive swing on the source resistor "following" the positive swing on the input keeping the differnce small and within the input clipping threshold. Does this attenuate the input signal (eg going into an output buffer) or does it allow a larger input to pass without clipping.

Is there a more indepth tutorial that is newbie friendly that will explain how negative feeback or source degeneration helps the input of larger signals without clipping into both opamps and transistors?

Thanks. 

[MaxPower]

Texas Instruments has a couple of pdfs on op amps which may be of use:
http://www.ti.com/lit/an/slod006b/slod006b.pdf  Op Amps for Everyone Design Guide (Rev. B)
http://www.ti.com/lit/an/sboa092a/sboa092a.pdf  Handbook of Operational Amplifier Applications


Electronic Principles by Malvino is a pretty good place to start for transistors and op amps imo. Older editions can be had for around $5-$10 on Amazon (last time I checked anyway). I'd also recommend Transistor Circuit Approximations also by Malvino if you can find it cheap.

[Thecomedian]

http://www.youtube.com/watch?v=9X0I6hO3prY

Source degeneration appears to make the amplification of a FET transistor linear if Rs is high enough, by swamping the effect gm has on amplification so that it's a minimal if almost completely gone effect on gain and introducing non-linearity. However this also greatly reduces gain, like a bipolar transistor.

http://en.wikipedia.org/wiki/Negative_feedback_amplifier

http://www.ti.com/lit/ml/sloa077/sloa077.pdf

It will probably be great help to you to consider simple one transistor amplifier and its voltages and currents. Voltage = Electromotive force, and causes current to flow based on how much or little resistance is there. If you have an amplified signal that is 180 degrees out of phase and it is fed back by a resistor pass into the original signal, it'll directly oppose changes in voltage, and therefore changes in current, making both smaller. If the feedback is in phase with the original signal, it's based on the voltage difference being minimized, as you point out. minimal voltage difference means low current flow, because Voltage is measured as a DIFFERENCE of two points. a 9V battery has a difference of 9V from + to -. A 100 ohm resistor will have less current flow through it from a 1.5V battery.

For negative feedback by bipolar transistor, as an example, if Emitter is tied directly to ground, the voltage difference will drop completely across the transistor for Collector to Emitter. The controlling signal at the base will influence the resistance in the transistor to go from very high to very low, and without any negative feedback, proper biasing of a transistor to sit at a quiescent point and work in Class A amplification (where the full signal is recreated by the DC current) is extremely difficult and subject to changes in temperature, among other things.

Any working amplifying schematic you see in these forums or for pedals anywhere else has some form of negative feedback, whether it comes from Collector to Base as a BIGASS resistor, or sits on the emitter. The Collector to Base resistor must be large not only to make the path through the transistor look like a short circuit in comparison, and thus the signal takes it for useful amplification rather than passing through C-B resistor directly to output unamplified, but to send back a fractional amount of the already amplified signal that is 180 degrees out of phase in order to reduce the amplitude/current of the incoming signal until it settles on an equilibrium point.

Emitter feedback works on the principle of keeping voltage drop between collector and emitter within a certain range.

http://www.allaboutcircuits.com/vol_3/chpt_4/12.html This may be the most newbie friendly.

[teemuk]

When we use source degeneration, it allows a larger input that usual to pass without clipping. ... Does this attenuate the input signal (eg going into an output buffer) or does it allow a larger input to pass without clipping.

I'm not quite sure what you mean but negative feedback (e.g. source degeneration) primarily reduces gain. Since gain is reduced the circuit tolerates higher amplitude input signals without exceeding the clipping threshold. For example, if we have a circuit with a clipping threshold of, say, 10 volts and circuit's gain open loop (sans feedback) is x10 and closed loop (feedback applied) x5 the open loop circuit clips at input signal amplitudes of 1V while the closed loop circuit clips at input signal amplitudes of 2V.

So, no attenuation of input signal, just reduction of gain.

A secondary, much lesser, effect is that the overall "area of operation" is linearized so the circuit might achieve slightly higher clipping thresholds than a circuit sans negative feedback. Strong emphasis on the word "might".

[Dylfish]

Thanks!

I've been busy reading through Electronic Principles by Malvino and some things are falling into place finally. I am terrible at explaining things with words, so the question I'm about to ask will have a few images to help me.



I understand that having a gate voltage more than 0 (unlike in self biasing) will allow you to use a larger Voltage on source to achieve the same operating point.

Eg.
Instead of Vg = 0 & Vs = 1 to achieve -1v. I could use Vg = 3v & Vs = 4v to get the same result. How does having a larger source voltage increase the tolerance / headroom in which the input has?

I was under the impression that Vgs = 0 is always IDSS / Saturation and Vgs(off) is Cutoff. The picture below is using values I've measured with a J201. This is just an example if on an output buffer you wanted the buffer to stay clean with a 3v p2p input.



Either way, on the input this larger signal would cause clipping. How does the source voltage change this since Idss and Vgs(off) are set in stone.

I have read how negative feedback deceased open loop gain by directly feeding back a fraction into the input on an opamp. I am aware that gain (gm) is decreased by source degeneration, but if an input signal is driving into cutoff and saturation back and forth doesn't this become irrelevant?

Sorry about the questions, but i'm trying to use this on an output buffer and since I have input signals larger than the VP on the devices i have, I'm unaware if the source voltage is decreasing the input signal so the AC on Vgs stays between 0 & Vgs(off) or if something else is happening.

Is my only option to use a FET with a larger Vgs(off)? I'm using this opportunity to learn more about the situation.

Thanks!

[bool]

The buffer's ability to swing negative signal will be low if you don't pull the gate up. Or you should use fets with large enough Vgs(off) to pass your signal.

If you want to squeeze max headroom out of your circuit, you should bias it so that your fet's source idles at approx Vb/2, so the gate bias voltage should be Vb/2 - Vgs(off) (for Jfets and depletition mode mosfets).

Or Vb/2 + Vbe for bjts, or Vb/2 + Vgs (for enhancement mode mosfets .. like 2n7000 etc).

[Dylfish]

Sorry, what's vb? I'm assuming base (on a bjt)?

[bool]

it's V+, supply rail voltage

[R.G.]

How negative feedback works:
(1) The amplifier must have at least an inverting input. It may also have a non-inverting input, but this is not pertinent to the feedback setup.
(2) The amplifier inside the feedback loop has a large gain, which is not affected by the feedback.
(3) Negative feedback circuits arrange to subtract a portion of the output from a portion of the input signal.
(4) This subtraction is not perfect; there is some error residue signal from subtracting B*output from A*input.
(5) The output signal is the open loop gain times the error residue. So the amplifier input sees a signal that is 1/(open loop gain) of the size of the output.
(6) Some means of biasing the amplifier is needed. This may or may not depend on the feedback setup. For opamps, it does, as they amplify the difference between the + and - inputs. For opamps, the output will attempt to settle at the feedback gain at DC times the +input signal. If there is a DC blocking cap in the feedback network to force the DC gain to unity, then the opamp will bias at the noninverting input voltage +/- the error voltage from amplifying and the internal offset errors in the amp.

For biasing bipolars and JFETs, there is more work at biasing because the "noninverting input" is the emitter or source, and there are DC offsets and such in the device itself that make the DC biasing of an opamp look easy.

[rring]

I guess you don't need an inverting amplifier all the time(most of the time this makes sense) you really just need to introduce output out of phase with the input - you could use a transformer for example.

Just for completeness let me point out that negative feedback affects more than gain. The traditional mathematical way to analyze feedback is with two port parameters.

With two port parameters you can analyze very complicated circuits by simply measuring input to output relationships. You look at input v to output current , input v to output v, input current to output v, and input current to output current..which two port parameter analysis makes the most sense to use all depends on the circuit.


source degeneration is series/series feedback, there is also shunt/shunt, shunt/series and series/shunt. A traditional inverting op amp configuration is shunt/shunt.

what does this affect besides gain? shunt lowers impedance and series increases impedance. With source degeneration you  increase input Z(not very meaningful with JFET) but very significant with BJT. You also increase output Z. Shunt/Shunt feedback can be created by feedback from Drain to Gate or Collector to  Base. This will lower gain and reduce Input Z and Output Z.

[R.G.]

Just for completeness let me point out that negative feedback affects more than gain.

That's very true. It affects almost everything, and in a preponderantly good way.

what does this affect besides gain? shunt lowers impedance and series increases impedance. With source degeneration you  increase input Z(not very meaningful with JFET) but very significant with BJT. You also increase output Z. Shunt/Shunt feedback can be created by feedback from Drain to Gate or Collector to  Base. This will lower gain and reduce Input Z and Output Z.

There is a huge amount of detail on this, OK. We spent a good many lecture sessions on it back in the day.

I was trying to get across the minimum info that would help dylfish - he's been having issues with learing biasing and signal level effects in feedback amplifiers.

@Dylfish - as noted, there is a lot more to this.

[PRR]

> I have input signals larger than the VP on the devices i have

Say Vp is 1V. Say you could find 100V JFETs, just to make the point very clear.

[Thecomedian]

> I have input signals larger than the VP on the devices i have

Say Vp is 1V. Say you could find 100V JFETs, just to make the point very clear.

The same principle applies to Tubes and I think BJTs as well. Voltage is all relative and that's mostly what matters.

[Dylfish]

> I have input signals larger than the VP on the devices i have

Say Vp is 1V. Say you could find 100V JFETs, just to make the point very clear.

In all seriousness i think i have really tried to look into it all way too indepth and at the same point "drowned" myself in information that just adds to the confusion.  This crude drawing just explained alot of things that i've been bogging myself down with, needlessly.

This whole time i've been thinking the below is just automatically trhowing it into clipiing and saturation, when it's not Vg that matter, but Vgs. Sorry for all the heartache.


Thanks everybody

[PRR]

> same principle applies to Tubes and I think BJTs

Tubes and JFETs are practically the same. If you DC-tie the grid to zero, you find a small positive voltage at cathode (gate, source). This is simple and sufficient for SMALL signals. If you find 1.0V at Source, you can swing maybe 0.9V negative peaks with some distortion and <0.5V neg-peak with low distortion. (Positive swings are not a problem for reasonable plate/drain suply voltage.)

Quite often we need/want "more". Then a cathode-follower needs the input biased-up somewhat more than the negative peak input swing. (Which generally implies an input coupling capacitor.) As a simple concept, the optimum may be half-way up the available supply voltage, as shown by my 50V bias under 100V supply. If any higher, now you lose the positive peaks. The "half-way" may have to be adjusted for heavy loads. If signal peaks are much less than half-supply, you could just use any convenient medium voltage.


OTOH..... with BJTs under a single supply, you never tie the base to zero volts. This simple technique fails utterly. A zero-biased BJT will stay "off" until the input exceeds 0.5V. Small input signals don't come out. Large input signals are brutally hacked-off below the navel. (Yes, this is used for distortion effects, or gating, by intent or by mistake. Also some leaky old BJTs may be used so it appears there is no deliberate bias but really their leakage gives some.)

[Dylfish]

This is one follow up question that may be the reason I've stuttered on this...

When reading about feedback, most, if not all examples I've seen are for Opamps. They show a physical connection from the output pin back to the input, Which is easy enough to understand.
Such as (for example):


When looking at Fet's I've been having a harder time visualising it. This morning I was thinking about KVL loops and thought this is may be my oversight on my behalf. Please correct me if im wrong or thinking about this too hard.
eg:


I was wondering how does the Voltage from the source "reenter" (so to speak) the input to create the feedback (as with the opamp)? Is it like I have sketched on the above? The thought that was it went back up through Rg to the input. (So Vin -> Gate -> Rs -> Rg -> Vin)
The feedback principle itself is fine, it's just the implementation.

Cheers

[R.G.]

I was wondering how does the Voltage from the source "reenter" (so to speak) the input to create the feedback (as with the opamp)? Is it like I have sketched on the above? The thought that was it went back up through Rg to the input. (So Vin -> Gate -> Rs -> Rg -> Vin)
The feedback principle itself is fine, it's just the implementation.

You need to read about series versus shunt feedback methods. There are two ways.

In the case of your picture, the actual signal the FET sees is the difference between the gate and source; that is Vgate-Vsource, which gets shortened to Vgs. Rising gate lets more current through the channel, which raises the source, too. The source voltage "reenters" by raising the source and this increase manifests as an increasing value subtracted from the gate voltage. It doesn't have to reenter from a loop.

In effect, the gate and source are a crude form of differential amplifier, amplifying only the difference between the gate and source. And in fact, you can hold the gate fixed and insert a signal at the source. This will be amplified and pass out the drain too. It works the same way, as the change in the source voltage with respect to the gate voltage is what drives the channel resistance to change.

[Dylfish]

In the case of your picture, the actual signal the FET sees is the difference between the gate and source; that is Vgate-Vsource, which gets shortened to Vgs. Rising gate lets more current through the channel, which raises the source, too. The source voltage "reenters" by raising the source and this increase manifests as an increasing value subtracted from the gate voltage. It doesn't have to reenter from a loop.

In effect, the gate and source are a crude form of differential amplifier, amplifying only the difference between the gate and source. And in fact, you can hold the gate fixed and insert a signal at the source. This will be amplified and pass out the drain too. It works the same way, as the change in the source voltage with respect to the gate voltage is what drives the channel resistance to change.

=( Here I was thinking this was too simple an explanation the hundreds of times I went over it in my head. That being said, If we want an output buffer to not distort any further at the end of a circuit, We would have to reduce Vin to within the Vgs VP constraints,(Via neg feedback) and therefore lose whatever is subtracted from Vin (raw in signal). So using a larger VP Fet is pretty much the only way to keep it signal clean and as amplified as previously intended.

Thanks RG =)

[R.G.]

I think so. At least within the constraints of using a simple self-biased JFET circuit. Large Vp moves the source up enough to not bang into ground so easily.

There are a couple of other things to consider. The higher the transconductance of the JFET, the closer the source voltage will follow the gate. If the source and gate are all balanced out with some Vgs between them, and a signal raises the gate, the source will rise because the gate has risen and decreased the Vgs, allowing more current through into the source resistor. The source rises until the increased gate voltage minus the increased source voltage causes a current that just keeps that changed voltage on the source. But since this is a higher current than it was sitting at before the rising signal, the Vgs must have decreased just a fraction to allow this increased current to flow.

The net result is that the gain of a simple follower is never truly unity. It's smaller by an amount depending on how high the transconductance of the device is. That is, how many more amperes of current flow for each volt of increase on the control voltage (Vgs in this case). Very high transconductance means gains closer to unity for a simple follower. Lower transconductance means gains notably lower than unity. This is the reason that bipolar transistor emitter followers have gains closer to unity than JFET source followers - they have a higher transconductance, so the error voltage needed to drive signal variations is smaller.

I think you might enjoy this: http://faculty.pnc.edu/jlerne00/ECET257/ Take a wander through module 2.