Learning resources for BBD and how they work.

[ThePastRecedes]

So I want to learn a little more about BBD. Is reading schematics and data sheets the only way to go? Googling hasn't been the most helpful in finding articles that explain this technology. Some thing like beavis audio but for BBD would be cool but I'm certain that doesn't exist. 

So can anybody point me in the right direction to learn more about this mystical technology?

[armdnrdy]

This was just posted on a current thread:
Download all six pages. A very informative article that I've "returned to" many times!

http://www.cjlectronics.com/tech_info/bucket_brigade_info

[Tony Forestiere]

I linked this same scan awhile back: https://dl.dropboxusercontent.com/u/3173950/SAD1024%20Blocks.PDF

[ThePastRecedes]

Thanks guys! you guys were fast. It looks like I'll have some reading when I get home!  Any more good readings would be appreciated!

[R.G.]

It's not partcularly mystical. They're called "bucket brigade devices" for a reason.

First, what is a bucket brigade? Back before municipal water systems with pressurized water and pumper trucks, if a fire broke out, people formed up into a bucked brigade. People lined up from the water source to the fire, and the guy at the water source dipped a bucket full(ish) of water and passed it up the line. Each person passed it on and the guy at the fire end threw it onto the fire. It was all they had. Obviously, each bucket suffered a time delay of N person-times being passed up the line, and each bucket arrived at the fire with the same water it started with, minus splashing and losses on the way.

Bucket brigade ICs use capacitors for buckets. They fill up the input capacitor with the input voltage, and then pass it up the chain one spot with each clock cycle. Bucket brigade.

Well, almost. The caps are the buckets, but since they really can't actually move the capacitors around on the chip, they move the voltage from one capacitor/bucket to the next. It's like a human bucket brigade, with each person having their own bucket, and pouring the water from one person's bucket to the next.

This is done with MOS transistors used as switches, and is why there are always (at least) two clock phases. On one clock phase, each station passes its voltage/water into a temporary holding bucket, then on the next phase each station takes the voltage/water from the holding station in front of it.

So the voltage coming in is sampled into an input bucket at the clock frequency, and the voltage going out is sampled out. The output voltage is not smooth, but is a series of stairsteps that approximate the input voltage, minus losses on the way. Yep, like people, some amount of the good stuff is lost in all the pouring back and forth into buckets.

At the end, all that stairstepping is smoothed out with an output filter.

The delay is equal to the number of holding stations/buckets times the frequency of the clock. If there are 100 people in a bucket brigade chain and they pass a bucket once each second, the water/voltage in any given sample of the pond gets to the fire 100 stations times 1/second, or 100 seconds later. If a bucket brigade chip has 1024 stages and is clocked 1024 times per second, the output is delayed one second. If it's clocked at about 1MHz, the output is delayed one millisecond, about. If it's clocked at 10Mhz, the output is delayed 100 uS.

All done. The rest of BBDs is the idiosyncrasies of exactly how they like to be kissed - er, clocked  , what power supplies, how the input and output are filtered to eliminate sampled-data frequency domain fold-over effects and such.  

[Mark Hammer]

BBDs are basically complex sample-and-hold units.  A synthesizer sample and hold takes an input signal (usually noise) and briefly opens up a "gate", that is made of a FET.  Whatever the voltage of the signal happens to be at that very instant is held in a capacitor.  The capacitor is effectively insulated/isolated by a FET on each "side" of it (i.e., VERY high impedance path so the voltage has nowhere to drain off to).  The sampled voltage is used to control something else, but cannot be held indefinitely.

BBDs do the same thing.  They provide a brief snapshot of the input signal - a sampled voltage.  Instead of a single capacitor where the voltage is held, however, they have a nifty system of coordinated FET "gates", controlled by the complementary (tick and tock) clock pulses.  Much like a system of canal locks where a boat sits in a confined area while that area either has the water level lowered or raised to match the next stage before being allowed to pass to the next stage, the sampled voltage is allowed to charge up the next tiny capacitor in the sequence, without affecting anything else before it or in the stage after the next one.

Where a storage capacitor used in a S&H for a synth may be several microfarads, and allowed to be of any material that has low leakage, regardless of how big it would have to be, the storage caps on a BBD are very small and very low value.  This means that will not hold the signal (sampled voltage) for very long.  Plus it also takes time to charge up a cap, so you don't want them to be too large in value anyway.  What this means is that the sampled voltage has to get passed along pretty quickly from cap to cap (stage to stage), or else it drains away and the output stops resembling the input.  At the same time, there are limits to how fast it can take what it is in one storage cap and use that to charge up another.  So, it can't go too fast or too slow.

BBDs make efficient use of the clock that steps them through their paces by allowing each clock pulse to do "double duty".  Each BBD has two parallel chains of storage cells with their individual gates.  Where the "tick" pulse tells one of those chains to acquire a new voltage, it tells the other chain to transfer the voltage it has stored in its cells.  When the clock goes "tock" the roles within each series of cells changes.  The signal is divided into interlaced snapshots, and then stitched back together - like a deck of cards split in half and quickly shuffled with your thumbs - at the output.  Higher quality delay circuits generally include a trimpot on the outputs, to make sure that the two complementary halves of the signal are matched for amplitude.

Because no single BBD can be clocked in a fashion that allows it to be a "universal" delay (i.e., anything from .1msec out to seconds of delay time) this is why there are BBDs of very different storage capacity, from 256 stages/steps (generally the shortest for audio purposes) out to 4096 stages/steps.  Between selecting the storage capacity, and clock rate, a range of desired delays can be obtained.

There, that's a good complement to the posts up already.

[DrAlx]

I just skimmed through the article by Ray Marston (the scan of 6 magazine pages) and found an error on page 6.
When describing the pre/post BBD low pass filters, it says the filter cutoff needs to be at least 1/3 below the maximum clock frequency.
That should have said minimum clock frequency. 
I'm assuming he's used a factor of 1/3 instead of the theoretical value of 1/2 in order to provide some margin in case only a first order LPF is used.
I've seen some designs have even looser filtering than that.

[Lurco]

I just skimmed through the article by Ray Marston (the scan of 6 magazine pages) and found an error on page 6.
When describing the pre/post BBD low pass filters, it says the filter cutoff needs to be at least 1/3 below the maximum clock frequency.
That should have said minimum clock frequency. 
I'm assuming he's used a factor of 1/3 instead of the theoretical value of 1/2 in order to provide some margin in case only a first order LPF is used.
I've seen some designs have even looser filtering than that.

One third of the min. clock frequency, not one third below it.

[DrAlx]

I just skimmed through the article by Ray Marston (the scan of 6 magazine pages) and found an error on page 6.
When describing the pre/post BBD low pass filters, it says the filter cutoff needs to be at least 1/3 below the maximum clock frequency.
That should have said minimum clock frequency. 
I'm assuming he's used a factor of 1/3 instead of the theoretical value of 1/2 in order to provide some margin in case only a first order LPF is used.
I've seen some designs have even looser filtering than that.

One third of the min. clock frequency, not one third below it.

Not sure what you mean, but I definitely meant below.
If you have a clock of 90 kHz then all signals above 45 kHz will alias, so you should get rid of them.
Marston is saying get rid of even more just to be safe, i.e. get rid of everything above 30 kHz.
In fact the the lower the cutoff the better, so long as you are not throwing away useful audio.
So in my example, I would set the cutoff at around 20 kHz if the input signal is for general audio
and you can go lower still if the input is just from a guitar.  As an example, a recent posting on another thread shows the EHX Flanger Hoax has
input LPF with cutoff frequency well below 10kHz.

[mth5044]

The link from armdnrdy was informative!

Is there any readable info about the clocks and how to modulate them (VCO/LFO/etc)? I guess that's getting more specific than how a BBD works, but deciphering what is going on in a chorus/flanger/delay's time keeper is a major brain zapping task without some written words. Danke!

[DrAlx]

Is there any readable info about the clocks and how to modulate them (VCO/LFO/etc)? I guess that's getting more specific than how a BBD works, but deciphering what is going on in a chorus/flanger/delay's time keeper is a major brain zapping task without some written words. Danke!

There are lots of approaches for producing the clock signals.

I would take a look at the LFO and VCO used in either the Deluxe Electric Mistress (DEM) or 9V Electric Mistress.  See the EM3207 thread for a version based on the 3207 BBD.
The reason I suggest that particular combination of LFO and VCO is...

1) The LFO is just a standard triangle/square wave generator using two op-amps.
    It is a common circuit and you can search the web for lots of explanations for how it works.
    The triangle wave is the control voltage for the VCO.

2) The nice thing about the VCO of the DEM is that the control voltage (CV) maps linearly to the delay produced by the BBD.
    So the LFO triangle wave will cause the BBD delay to be a triangle wave too.
    i.e. the delay time will rise and fall linearly with the sweep.  This will sound pleasing.

     Many "other" flangers use VCOs that don't have this nice property built in, so a non-linear element is introduced to compensate
    (e.g. using the control voltage to control a FET acting as a variable resistor in the VCO).
     You may see references to sweeps needed to be "hypertriangular" although I find that terminology misleading.
     It is just another way of saying that these "other" VCOs need a non-linear element in order to get a nice sweep.
     It's not an issue with the DEM, so you can forget about it.
     
3)  The VCO is quite easy to understand. 
      There is a small capacitor (the clock capacitor) that is repeatedly charged and discharged.
      A transistor current source charges the capacitor at a constant rate, causing the capacitors voltage to increase linearly in time.
      The capacitor voltage is monitored by a comparator chip.
      When the capacitor voltage matches the CV voltage (from the LFO), the comparator quickly discharges the capacitor through a diode, and the process repeats.
      Each time the capacitor discharges, it triggers a flip-flop (which produces the clock signals for the BBD).
 
      So the triangle wave CV from the LFO just sets a "target" voltage for the capacitor to reach.
      If the CV increases linearly, then ...
           The time taken for the cap to reach its target voltage will increase linearly.   
           So the time between the clock pulses will increase linearly.
           So the overall delay produced by the BBD will increase linearly.

     Notice how everything here is linear (which I think makes it easy to understand).

[mth5044]

Wow! Thanks for all the information DrAlx!

The LFO is familiar to me, especially the two opamp variety. What the interaction with the VCO is is what I am trying to understand. Below I've linked to Mad Beans' version of the DEM/Current Lover and a retrace of the EchoFlanger/PolyChorus by Nelson.

http://www.madbeanpedals.com/projects/CurrentLover/CurrentLover.pdf
http://www.google.com/url?q=http://guitar-gear.ru/forum/index.php%3Fapp%3Dcore%26module%3Dattach%26section%3Dattach%26attach_id%3D21075&sa=U&ei=mBuzU-ewMNaSqAaoxICwDw&ved=0CBwQFjAB&usg=AFQjCNEWbL-OGx7keFQuyOBh32zuKLy_8w

The echoflanger is an earlier schematic before he simplified the switching, but the output of the lfo essentially either goes to R12 or the C1/R7 junction. Let's say it's going on to the C1/R7 VCO part.

The two seem very similar to me, different values in the LFO and the DEM has C16 to smooth the triangle a bit, possibly? The EchoFlanger also has some extended circuitry to control the width and tune - somewhat comparable to the DEM range control. Then we come to the transistor you had talked about and the associated timing cap. The DEM has a 22p while the EF is 47p or 197p when that extra 150p is switched in (assuming for chorus mode). One thing I was curious about is what the relationship between the timing cap and the delay time is? How drastic is 22p to 47p? Must be noticeable because I've seen some projects that switch this cap, but how does one figure out how it changes the delay time? There must be a series of equations somewhere.

Another question I have is about buffering the clock signals. How necessary is it to have all those buffers on the DEM? A single then two in parallel. Compared to the EF, which splits the clock into two separate clock lines, the DEM has way more buffering. Is one good enough as in two of the parts of the EF, but all of them used because they are there for the DEM?

Does the 4013 chip invert one of the clock sends? I believe I read that the BBD needs two clock signals out of phase.

My final bit of questioning is what voltage swing and bias is needed for the LFO? Does it matter? Simulating both shows slightly different wave forms. The EF is very pointy triangle and the DEM has slightly rounded edges but straight rises and falls (technical names, I know). The DEM has a range of ~0.02 to 2.9Hz while the EF has ~0.03 to 3.6Hz. So it seems like dedicated flangers need to have a lower Hz / faster speeds for a more desirable sound while the EF may compromise to get both rates from one turn of a knob.

Anyway, the sim showed that the EF was biased around 7.5V with a 0.25V swing in either direction. The DEM was at 1.5V with a 0.5V swing in either direction. The EF is powered by 15V, so the 7.5V seems right in the middle, but the DEM is at 9V, so I expected 4.5V bias. Does the voltage fed to the VCO matter? It seems like an LFO with a more broad range of V would produce a larger swing in delay time based on your cap charging explanation, but is the difference between 0.25 and 0.5 noticeable?

Thanks for taking the time to read all that.   

[DrAlx]

One thing I was curious about is what the relationship between the timing cap and the delay time is? How drastic is 22p to 47p?

Like I said in my simplified explanation, everything is quite linear..  For the same charge current, increasing the clock cap increases the min and max charge times.  A capacitor that is twice as large takes twice as long to fill to a a particular voltage level.  So increasing the cap will increase the clock period, and therefore the delay.
So for example if a 22pF gives a sweep with delays that go from 1 ms to 4ms delay, then increasing it to 47pF will make the delays go to a larger range e.g.  2ms to 8ms.
The Current Lover is very very similar to the EM3207.  On the EM3207 thread there is this graph showing how changing the clock cap changes things.
http://www.diystompboxes.com/smfforum/index.php?topic=91981.msg799053#msg799053
Remember it's not just the cap that controls the delay.  Using a weaker charge current is like using a larger cap.
And then there's the control voltage.  In the EM, the sweep ratio (i.e. ratio of max to min delay times) is not so much controlled by the charge rate and cap value, as by the max and min LFO voltages.  I describe a mod you can do to the LFO to give wider sweep ratio in the EM3207 thread (somewhere near the end pages of that thread).  I'd recommend you go through that thread, even though it's quite long.  You'll probably learn quite a bit.

Another question I have is about buffering the clock signals. How necessary is it to have all those buffers on the DEM? A single then two in parallel.

Depends who you ask.  I thought they made a difference but when I recorded two samples to do an A/B test with and without clock buffers, I couldn't tell if any difference was down to my playing or the buffers.  I would need to do a proper test by measuring the frequency response.  The point of  the buffers is to overcome the input capacitance on the panasonic delay chips so they can be clocked past their spec. I'm undecided on whether they are worth including.  The circuit will work without them.  Oh and by the way, you need the 4049B chips, NOT the 4049UB chips shown in that echoflanger.
schematic.  It really would be pointless putting those in.  Those UB chips are unbuffered CMOS, so they won't do anything to sharpen the clock wave form.  That's right, they are unbuffered buffer chips!
EDIT: Beware when trying to buy 4049 buffer chips on Ebay.  Some sellers are sloppy with both the way they name the chips and the photos they use.   e.g.  I've seen some advertised as 4049B in the title but the picture shows the chip is in fact a 4049UB.  Pretty much all the Ebay listing I've seen have been for UB chips.

Does the 4013 chip invert one of the clock sends? There are two outputs I believe I read that the BBD needs two clock signals out of phase.

The 4013 outputs both clocks.  (The Q and Qbar outputs from a flip-flop).

My final bit of questioning is what voltage swing and bias is needed for the LFO? Does it matter?

The LFO voltage in the EM (i.e. the triangle wave at the opamp output ) isn't used directly on the VCO.
It gets scaled to an appropriate range of values first.  It's that range of values that matters.

For the EM VCO, the control voltage can't go too low or the VCO will stop oscillating (it can only go so fast).
Generally for flangers, you want a delay time from around 1ms (less is even better) to 10ms.
I've found that the EM3207 circuit values and a 47pF cap, the control voltage can't go much lower than around 0.8V (for the shortest delay times).

[mth5044]

DrAlx you are fantastic. I had thought that right after the LFO was where the VCO started, but that is where the scaling begins! I will have to simulate it and see what happens. I will get to reading through the link you provided as well. Thanks a ton.

[mth5044]

Continuing with BBD circuit questions! Referring back to the EF schematic I posted earlier. Right after the first compander half, the signal splits, one going to a LPF and the first MN chip with a BBD level control, the other to the switching IC. The IC switches between sending the pre-filtered signal to the input of the second MN chip and the signal coming out of the first MN chip. Makes sense to get different delay times, but how is the signal going straight into the second MN without filtering or level control? What are those two 100k's doing with the Vbias? Something seems very strange.

[DrAlx]

... but how is the signal going straight into the second MN without filtering or level control?

I am guessing level control may be needed because the compander output range may be too large for the BBDs input.
Why only one gain control?  Check the 3007 datasheet and you'll probably find those BBDs have very small gain/loss
so if signal has good amplitude for the first it will be OK for the second.

For BBDs in series clocked by the same clock, you are sampling the signal at the same rate and the BBDs are sort of acting like a BBD of double the length. 
You just an anti-alias before the audio goes into the (first) BBD.  The second BBD won't introduce anymore aliasing ('cos sample rate it same as first).

What are those two 100k's doing with the Vbias?

Each 100k resistor couples Vbias to the input.   The 100k works as part of a high pass filter with the preceding 0.1uF cap (cutting audio below 16Hz).
Changing the 100k to simple wire would not change the bias level at the BBD input but would filter out all the audio.

[mth5044]

As always, thank you DrAlx.

Something is stuck in my brain cogs, making me not quite understand what's going on. I've drawn out the two seperate circuits depending on what position is switched.

The first one is when the 3007's are in series - this one that makes sense. In this case, the timing cap equals 197pF, meaning it's in chorus mode. There is a level control and a filter before the string of 3007's which seems normal to me and what you had commented on previously.


The second one is where I have problems making sense. The timing cap is at 47p and with only one 3007 in the signal path, we must be in flanging mode. So why doesn't this 3007 need an input level control or the heavey Sallen Key-esq filtering that we needed in chorus mode? 

[DrAlx]

I wouldn't worry about the filtering and level control.
Firstly, that circuit you are looking at is the first flanger or chorus I've come across that has any sort of level control before the BBD.
I'm not convinced why it is even necessary.  If the reason was to "correct" the gain from the compander chip (which is what I suspect) then that is not the way I would have gone about things.  It should be possible to set a correct gain and output bias by connecting appropriate value resistors to the compander. See the application notes...  http://www.onsemi.com/pub_link/Collateral/AND8159-D.PDF.

If your second picture is correct and those two delay lines are mixed together then there is no relative delay between the lines so you won't get flanging.  Maybe they're using the two BBDs to give parallel multiplexing (i.e. higher sample rate for the same clock).
Even if  that were the case, you would expect to treat both lines in the same way.  Maybe the circuit you are looking at is not a good choice to learn how how to do things.  Take a look at some of the other chorus and flanger effects and you'll find that many don't bother with companders and some don't have heavy filtering either.  I would treat companding, level control, and heavy filtering as optional extras.  You may need heavier filtering if the clock rate goes low, since BBD clock noise increases for lower clock rates.

[mth5044]

Thanks for the info. The past few weeks I've been studying flanger and chorus pedals and they all seem pretty straightforward at heart with various 'optional extras' as you say. The EchoFlanger seemed like a bit of an enigma.