Possible to bias jfet at gate?

[nsteen]

I'm interested in building a simple boost using an mpf102 but would prefer to have no resistor between v+ and source as I would also like to connect the drain to the buffered output rather than make it true bypass.

Is this a silly thing to do? Admittedly I am a newbie so knowing stuff about how to determine the proper bias for a jfet is kind of beyond me. The idea was to make a one transistor boost using the mpf102 and a charge pump to run it at ~24v kind of like a SHO but with more of that echoplex tonality/vibe.

Thanks in advance for any and all help.

[smallbearelec]

I'm interested in building a simple boost using an mpf102....The idea was to make a one transistor boost using the mpf102 and a charge pump to run it at ~24v kind of like a SHO but with more of that echoplex tonality/vibe.

Try some of the experiments in this article:

https://www.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm

You'll learn how a JFET works and how to line one up for the gain you want. The principles apply as well at higher supply voltages.

[nsteen]

Thank you! I've been looking for instructional resources but I haven't been good at finding them.

Awesome sauce