Quick Tim Escobado Schematic question.

[XXISouthpaw]

Just wondering before I go breadboarding this circuit, is there no electrolytic capacitors in this circuit?

Also, with the CD4070 chip, I'm  anyone able to give a rough idea what's going on inside it? Feel it'd be a good excercise to really dig into some of Escobado's schematics.



Cheers in advance!

Chris.

[GibsonGM]

The 22uF cap is electrolytic.   Looks like that's it! 

The chips is an 'exclusive OR gate'.  It's a set of logic gates (see the truth table).  More info here:  http://www.futurlec.com/4000Series/CD4070.shtml

[XXISouthpaw]

Sorry, should have said I had the datasheet for the pin, don't quite get how it's actually effecting the audio though.

and for the pinout section, is this how I would go about it? (A+B=J for the first Gate, E+F=L for the second Gate.)

[anotherjim]

You can slip into Boolean algebra if you want, but that won't really help here.

The Exclusive OR is a logic comparator. It checks for a difference between the inputs. For an 2 in X-OR gate, the output is only high if only one of the inputs is high - doesn't matter which input as long as one is low and one high. Any other condition of input (both low or both high) the output is Low.

The 100k and 2nF cause a delay in level change to one pin. So as the squared up signal from the first gate changes from high to low or from low to high, for the duration of the time constant of the RC network, there is a difference between the levels on each input of the second gate. This results in the second gates output switching high until the timing network completes and both inputs have the same level when the output switches back to low.

The result is 2 positive pulses coming out for every cycle of the input signal - Frequency doubling!

[GibsonGM]

Good breakdown, Jim.  Not being a 'logic guy', that was helpful to me, too! 

[PRR]

> ...Boolean...won't really help ... comparator ...... 100k and 2nF ...... doubling!

Thanks. Neat elegant explanation.

The question is "quick" but the answer is looong, especially since it isn't working as a classic logic comparator but an analog comparator with funny rules. You put it very well.

Observation on the original: Pin "A" (in Chris' mark-up) has no explicit DC bias. Unconnected CMOS inputs can assume "any" DC voltage. This is usually a Bad Thing. Circuit action is undefined. I guess in this case we do not care what the static no-signal condition is. When the input booster slams signal at it through the cap, the CMOS input hits on both internal input protection diodes, and for music-like waves will tend to self-center around half supply voltage. From there, operation is pretty well defined, within the un-defined variations of musical waves.

[anotherjim]

Paul is right about the conditions on input A - it's a quick & dirty "get's away with it" thing.

I'd suggest an improvement would be to add a Schmitt trigger action to the first gate. A series resistor to input A (say 82k) and a feedback resistor (say 100k) from J to A. The first gate will now remain in the last state it changed to when there's no signal - it's stable. You can tune the sensitivity of the trigger by changing the ratio of the values of the 2 new resistors. Just keep Feedback R larger than Input R.

BTW, this kind of doubler works best with a good, vertical edged 50% duty cycle square wave into the second XOR. The (possibly) bad thing is that the output only has a 50% duty cycle at one input frequency (because the positive pulse width is fixed by the RC delay time). This being music, that's not necessarily a bad thing, but what if you want to do it again for another octave up? It will work, but now the pulse width will be really narrow most of the time and the output may be much less worth listening to. But, it will happily clock a divider such as a 4013. So then you can have an octave up with a 50% square at all input frequencies.