Flanger clock idea...

[Scruffie]

Just as thought experiment in 'reducing waste' I was thinking about the A/DA flanger clock circuitry and how most of the 4007 goes to waste and I came up with this idea.

In the A/DA the 4007 is used as the variable element which works well, then the 4047 is used as the clock and we buffer it with a 4049 to get over the 300X series clock pin capacitance.

Here i've stuck with the 4007 as the variable element but instead of half the chip going to waste, it's set up as a CMOS multi-vibrator, which gives a single phase clock, but not a very good square wave, which the BBD requires for the best performance.

So then instead of using all 6 inverters of the 4049 as buffers i've just gone with 2 inverters in parallel per clock line and used the 2 spare inverters as a CMOS flip-flop which gives us our 2 phase clock but I suppose the question is, how good a square does an inverter based flip-flop provide? 

[anotherjim]

That 2 inverter latch has me puzzled. I think the 2 diode feeds should be separate Set & Reset inputs. Feeding them together just looks like making an over-ride function, not a latch?

The jury could, I think, still be out on how much current drive is really needed in practice for the BBD clock, It might just be enough to use both halves of a 4013 D-type in parallel with /Q's feeding D's to divide the osc output to 50% duty cycle.

[Scruffie]

That 2 inverter latch has me puzzled. I think the 2 diode feeds should be separate Set & Reset inputs. Feeding them together just looks like making an over-ride function, not a latch?

Crap you're right, shouldn't try and rely on my memory when doodling.

The jury could, I think, still be out on how much current drive is really needed in practice for the BBD clock, It might just be enough to use both halves of a 4013 D-type in parallel with /Q's feeding D's to divide the osc output to 50% duty cycle.

That, is besides the point