3 volt piezo buffer

[anotherjim]

Not many sub 9volt buffer circuits published. This is a basic J-fet, nothing special, but in view of the low supply V, bias is trim-able, so you don't have to select the transistor to get the best clean headroom. The one I built on perf uses a CR2032 lithium button cell in a plastic holder and the J201 is an smd one. High input impedance, so make sure the piezo/wires are well screened.

[GibsonGM]

Very nice, Jim.    A good addition for the on-board electronics list.

[Kipper4]

Nice little circuit Jim
Thanks

[samhay]

Would it not benefit from an input cap seeing as you have biased the gate above ground?

[anotherjim]

Sam:
Is an input cap is necessary for a piezo - it pretty much is a cap itself yes?

But you have me thinking - DC on the input cable could make it a bit microphonic? Hmmm....

I found the FET source voltage was too often very close to V+ with ground referenced bias. Seems to me, this becomes more of an issue the lower the drain (supply) voltage is.
If I fitted an input cap, it would be 1nF film. To stop the piezo (+) "floating", it would need a pull down resistor. If that pull-down were 10M, the net input impedance will be about 5M, still high enough I think. If it proves necessary, I'll update.

You may also notice there is no power filtering or polarity or input protection.
1   It's always going to be battery powered, and that is already a pretty good capacitor.
2   It's impossible for CR2032 to connect in reverse in a proper holder. Even if it was, the circuit is not damaged by reverse supply. Watch out for this if you build it -  it will still pass audio with reverse polarity! Guess how I know
3   It's always going to be connected to a piezo, so no input protection really required.

That said, to be a little more "professional", maybe a small series resistor should be in the output between FET source & 1uF cap - maybe 470R to 1K - to limit output fault current.

[PRR]

A piezo can be leaky and still "work". That skews your preset bias.

> FET source voltage was too often very close to V+

Because with large source resistor, happy bias Vgs will be very nearly Vgs(off). And Vgs(off) for many JFETs is 2V-3V, which on a 3V supply is like putting a 9 foot monster truck in a 7 foot garage.

You want to pre-select your JFETs for low Vgs(off).

[anotherjim]

Damn typos. R1 is 4k7. Sorry. Although I've tested 47k & it can work with that. I'll update the scheme soon.

Tried 3 different disc piezos and none of them change the bias when connected. If a piezo goes leaky, I'd rather it did show up as a fault, but it can upset the bias some without putting the source too close to either + or -. Adding an input cap is easy, but I'm doing without. Even with some cheap lapped screen cable (I don't recommend keeping the red/black wires some discs come with), the cable is not itself microphonic, although it can of course transmit vibration to the piezo if handled close to the disc.

[anotherjim]

Corrected...