Need some help understanding JFETs, Voltage and overdrive

[BuddyPrince]

Some day I hope to understand what you all are talking about.  :-)

[Rob Strand]

You know what, the more I think about the transistor action the less I believe it.  I believe the macro effect but not the mechanism.  Fig 2 in the paper shows the gate current increasing but the gain is *dropping* almost in proportion.  It's like there is a weak mechanism increasing the drain current by only a small amount despite the large increase in the gate current.

What I suspect really going on is when the gate forward biases it removes the lower part of the channel.  Imagine a line across the channel where that part of the diode, and diodes below it, are conducting.  The potential at that point becomes positive.  That makes the JFET look shorter.   With VDS present, normally the top part of the JFET channel is partially closed off.  When forward gate biasing occurs VDS is applied over a shorted region of the channel and this moves the partially closed part of the channel up towards the drain, chopping of less of the channel and allowing more drain current to flow.  Also, the effective VDS is reduced, as the JFET sees the VDS' where is the internal source point but S is the external source terminal.. Because of the forward bias S' is at a higher voltage to S.

[EBK]

Some day I hope to understand what you all are talking about.  :-)

Since we haven't even fully figured out what we are talking about yet, I'd say you are pretty well caught up.   

[Rob Strand]

OK I did a quick test in spice.

* Two JFET cases *
1) Nothing special.  single JFET, params tweaked to give roughly same curves as Cobbold for normal case.
2) Split JFET into three series JFETs (top/middle/bottom).  VP the same in each case as a first order approximation (VP depends on channel width).

* Results *
I(R1) is Id for Case 1  - Red
I(R2) is Id for Case 2  - Green
x-axis is VDS

The currents and voltages are as per the Cobbold paper.
The only difference is the normal case has a Vgs=0 and the forward case has an Ig=0.

Normal Case (gate reversed biased)



Forward Gate Case



* Models Used *
Single JFET
*2N2498 - Hacked  to match Cobbold paper for normal case
* Idss = 2.5mA, Vp=2.7; beta = Idss/Vp^2
.MODEL JP2N2498RX1 PJF(VTO=-2.0 BETA=601u LAMBDA=0.013 RD=1m RS=1
*+ CGS=10p CGD=10p IS=9.48E-15 )
* ** RJS 15/3/2018

Three JFETs connected in series, with gates tied together (top/middle/bottom).
Bottom JFET has RS=1 like single (remnants of playing around with RS)
Use the following three "hacked" models
.MODEL JP2N2498RX1_3A PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=0.1m RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )
.MODEL JP2N2498RX1_3B PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=0.1m RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )
.MODEL JP2N2498RX1_3C PJF(VTO=-2.0 BETA=1803u LAMBDA=0.039 RD=1 RS=0.1m
+ CGS=3.33p CGD=3.33p IS=3.16E-15 )

* Comments *
- Not a lot of difference achieved by splitting the JFETS  (I did try 10JFETs).
- The sloped parts at higher VDS are slightly different.  This behaviour is set by Lambda.
   I can play with Lambda but the key point is the shape of the curve is different.
- The forward case behaves slightly differently.  Id is a few percent higher for the split JFETs
- The currents in the forward case are smaller than the Cobbold paper and we do not see the big
  Id step for Ig=10mA.  The currents are however in the ball-park.
  I suspect the JFET diode model, which determines Vgs, has something to do with it.
  The real junction might have a softer characteristic and the ohmic series resistances will
   probably have a much more complex behaviour (such as spreading).
   Also we cannot change the softness of the diode knee in spice
  Changing the diode model can move the drain current up and down but it cannot stretch the 10mA case.
  All this is doing is changing Vgs set by the diode drop at a given diode current Ig.
- The case were Ig=0 produces a slightly higher current than the Vgs=0 case.  In effect Vgs is slightly
positive when the gate is left disconnected (maybe Vgs = 200mV into forward bias).

Other than the split model, this doesn't add much to the physical understanding.   It does highlight
issue modelling the Vgs diode under forward bias.

[Edit: The differences are due to splitting the diodes and lambda.]

[PRR]

I bent my snow-blower, but it still doesn't go off-track as far as you guys did.

The "limit" on JFET gate voltage is not zero but forward-diode, >0.5V. Nothing happens "at zero". The channel current continues to increase along the same curve as negative voltages.

If Vto is like 3V, another half-Volt is not a big deal, so this area is not usually used.

If you do use it, you must look at how positive you want to swing and how strong the signal source is.

_NO_ real signal is Infinitely Strong like a SPICE voltage source.

A guitar is at least 5K in bass and higher in treble. With pots and all, 50K may be a good approximation. Not of the actual with-guitar effect, but to show if your SPICE sim is totally lying to you (giving a right answer to your wrong question).

Take 50K and assume 1V peak guitar signal. That's less than 0.020mA.

The problem of course is that the forward diode will load-down the guitar on positive peaks. But up to 0.5V peak, not very much. However after experimenting with several JFET models I am unsure what the true gate current is. Adding a dumb old 1N914 diode G-S gives 11uA current at 0.5V peak, giving slight reduction which may be inoffensive on guitar.

The negative swing is the generally-understood quad of the JFET and will work fine.

So *for 0.5V signals* the zero-bias mode works "OK". We do not need to resort to old parchments speculating on more extreme gate abuse. 0.011mA gate current into channel working at 1mA-10mA, the gate injection is quite negligible.

The "problem" is that Idss of a same-number JFET will vary 3:1, the drain voltage is very uncertain. Some parts will bottom, others will top-out. Every one will clip different. Adding a source resistor allows this variation to be greatly reduced.

Anyhow... Here's the dubious SPICE plot of a JFET in the positive gate region. "Nothing happens" at Zero Vgs. Things keep climbing to 0.6V. Plotted at this scale, there's no real deviation to 0.8V (which may be a mis-model). Over 0.9V the gate current soars, all that flows to Source, and Drain current falls-flat.



So for "small" signals, zero-bias is not a sin.

For the "amplifier": I got quite a few different results with different SPICE models. All seemed dubious for Gate current so I stuck the diode on. The input distortion for 10K and 0.5V peak is visible but mild. The gate current is plotted *1Meg otherwise it would not show. The Drain voltage is not "centered" but this will vary about directly with Idss, and with Rd. The gain for these conditions is quite low. Actually <1 for this model, ~1.5 for another. The DC-blocked output of course follows the Drain voltage without the DC content.

[PRR]

KA7OEI's tests on a real JFET:

"As can be seen, as the gate-source voltage increases, the drain increases linearly - even after the gate-source diode junction starts to conduct:  In fact, there does not appear to be inflection of the drain current curve when this happens!"

[GibsonGM]

Some day I hope to understand what you all are talking about.  :-)

So do some more advanced DIYer's than you or I, Buddy!    Lucky for us, most of the VERY in depth stuff going on here isn't required to design and build really nice stuff.  Truthfully, we can do pretty well working with designs that have already been done for us.   

Paul, posting above, has often talked about the VERY convenient fact that most all of what we're working with has been exhaustively put together, improved upon, and is all right there for us to.....umm, borrow, ha ha.  Why would we re-invent something that was made 40 years ago, and works great??  We can tweak it, and make it sound how WE want it to, but the guts are already all set.

For good or bad, most of what myself and many others have done is learn the BASIC setups for each class of active device (mostly)...BJTs, opamps, jfets/mostfets, and tubes (triodes mainly).    Just take an easy circuit, like an LPB-1, and learn how that works, and what happens when you alter some of the components that affect bias, and so on.   Then find out how an opamp amplifies, how it is biased, how it is used as a buffer...same for mosfets, jfets.  Yes, you'll make mistakes, or get into conversations where you look at little....foolish, over something you might have missed, but nobody here will give you (too much) hell over it.   

You don't have to be Einstein to be able to WORK with these things, and you don't need to understand them at an atomic level, LOL!  It's daunting at first, but after a little while you will see how things repeat, how parts of circuits can be blocked out as something you can understand, and in little time it stops being a collection of "WHAT IS THAT?" and becomes "OK, they put a tone stack in there, followed by a gain stage".    Keep asking and learning, and shortly you'll be whipping up your own stuff, I guarantee it.  Maybe later you'll want to explore the intricate characteristics of these devices, which can be fun once you are very far inside.

[Rob Strand]

The "limit" on JFET gate voltage is not zero but forward-diode, >0.5V. Nothing happens "at zero". The channel current continues to increase along the same curve as negative voltages.

The bottom line is as Vgs becomes positive Id continues to increase past IDSS, yet still closely following the usual square law.  There's no kink from the perspective of Vgs vs Id.     If however if there is a finite source impedance the gate-junction with limit Vgs and that limits Id.    The open gate case is close to but not exactly the same as Vgs=0.

Interestingly Triodes behave quite similar to JFETs.   The triode grid diodes are a lot softer than the JFET diodes.
That affects how the diode interacts with the source impedance. 

IIRC, the Peavey transtube ckts use transistors and diodes.

For MOSFETs, Id keeps increasing as there's no diode.

[EBK]

I bent my snow-blower, but it still doesn't go off-track as far as you guys did.

There's an important difference:  If you push a JFET backwards, you just risk losing a JFET, but if you push a bent snowblower backwards, you risk losing a hand.   

[PRR]

In JFETs: If Oxner didn't teach it, it isn't worth knowing.

Oxner knew his salary depended on Siliconix selling a lot of JFETs, so he told every useful thing. (Evans was his boss.) Siliconix did eventually fail, but not for lack of trying.

Oxner does mention why forward Ig curves are rarely given. I suspect they only had a uni-polar supply handy, and taking forward curves would require wire-switching, and why bother?  The reverse-bias Ig numbers are SO much prettier (albeit along the same line). They set the JFET apart from the sucky BJT.



Oxner gives "typical" Ig curve to 0.360Vgs. Extrapolating we get 1uA at 0.6V. So JFET gate diodes are about 1000X less conducty than BJT diodes. At 1uA, Shockley teaches 26,000 Ohms diode impedance. Low for geetar, but 0.1uA gives 260K, and that would be 0.54Vgs. 0.50V would be near 0.025uA and 1Meg. So a +0.5V forward bias is still High-impedance by guitar standards. Especially since it is higher yet at 0.45V and dynamic music will be lower most of the time.

[Rob Strand]

Oxner gives "typical" Ig curve to 0.360Vgs. Extrapolating we get 1uA at 0.6V. So JFET gate diodes are about 1000X less conducty than BJT diodes. At 1uA, Shockley teaches 26,000 Ohms diode impedance. Low for geetar, but 0.1uA gives 260K, and that would be 0.54Vgs. 0.50V would be near 0.025uA and 1Meg. So a +0.5V forward bias is still High-impedance by guitar standards. Especially since it is higher yet at 0.45V and dynamic music will be lower most of the time.

That's a good point.  JFET are often used as low-leakage diodes.  It follows that for a given voltage the diode current is lower.  I extrapolated the graph the other way and hit about 1x10^-14 A which is quite typical for a JFET diode.

The slope of the graph gives the hardness of the diode knee, which is a little softer than a BJT.  (At higher currents the ohmic effects come into play.  Which is probably part of what we see in Cobbold's 10mA case.)

I suspect they only had a uni-polar supply handy, and taking forward curves would require wire-switching, and why bother?

It's easier/more accurate to feed in current and measure voltage.