The MXR Micro Flanger needs more highs

[Rob Strand]

Sorry Rob, but since when was 2usecs = 0.5msecs?

Sorry, 2us was the clock period and 0.5ms was the delay.

[Scruffie]

Any MN3xxx type chip does not take kindly to clock frequencies above 100khz unless there is a buffer/current-drive stage between the clock and the BBD.

Just to clarify here, as Rob & Tom just discussed, that's not really true, a HF-2 drives a MN3204 to 0.5mS which is around 500kHz and the reissue A/DA flanger drove a MN3010 to 700 something with just a 4047 without the 4049 used in the clones.

The BBD datasheets all state 100KHz as the upper limit (actually the MN310X series states 200KHz IIRC) but a 4047/4013 will drive a MN3X07 to 800KHz fine, it depends on the particular BBD clock capacitance for the upper limit.

There are other considerations though, namely the gain of the particular BBD at higher frequencies, a lot of the panasonic chips drop off horribly as they get higher which messes up the mix horribly.

[Rob Strand]

The BBD datasheets all state 100KHz as the upper limit (actually the MN310X series states 200KHz IIRC) but a 4047/4013 will drive a MN3X07 to 800KHz fine, it depends on the particular BBD clock capacitance for the upper limit.

There are other considerations though, namely the gain of the particular BBD at higher frequencies, a lot of the panasonic chips drop off horribly as they get higher which messes up the mix horribly.

I guess it has a lot to do with the clock driver chip being able to drive the capacitance of the BBD clock input.

For example the MN3204 quotes 200kHz max (5uS period) but it also quotes clock rise and fall figures of 500nS max.   The 500nS figure looks suspiciously like a nominal 1/10th the clock period (5uS/10 = 500nS).

The clock input capacitance as 350pF (max) and Trise=Tfall = 500nS (max).
Then we estimate trise = tfall = 2.2* Tau = 2.2*C *Rdriver  implying Rdriver = 650 ohms.

If the driver has better drive than that then the upper clock limit would be expected to increase.

[Scruffie]

The BBD datasheets all state 100KHz as the upper limit (actually the MN310X series states 200KHz IIRC) but a 4047/4013 will drive a MN3X07 to 800KHz fine, it depends on the particular BBD clock capacitance for the upper limit.

There are other considerations though, namely the gain of the particular BBD at higher frequencies, a lot of the panasonic chips drop off horribly as they get higher which messes up the mix horribly.

I guess it has a lot to do with the clock driver chip being able to drive the capacitance of the BBD clock input.

For example the MN3204 quotes 200kHz max (5uS period) but it also quotes clock rise and fall figures of 500nS max.   The 500nS figure looks suspiciously like a nominal 1/10th the clock period (5uS/10 = 500nS).

The clock input capacitance as 350pF (max) and Trise=Tfall = 500nS (max).
Then we estimate trise = tfall = 2.2* Tau = 2.2*C *Rdriver  implying Rdriver = 650 ohms.

If the driver has better drive than that then the upper clock limit would be expected to increase.

Pretty much, most of the clock chips we use have buffers built in (apart from the 4046 I think) even the complimentary ones but the datasheet spec doesn't consider the individual capacitance.

I think the limits are there because as I stated, a lot of the chips will produce poor performance at anything past that (why the variances are so wide between chips I don't know, the MN3004 for instance has a pretty bad insertion gain loss and drops off quite dramatically at higher clocks IIRC but the MN3007 gain is much more linear with more stages) but the point is the clock can do it and several production pedals show this, even using the MN3101/2.

[Rob Strand]

why the variances are so wide between chips I don't know, the MN3004 for instance has a pretty bad insertion gain loss and drops off quite dramatically at higher clocks IIRC but the MN3007 gain is much more linear with more stages

When I look at the datasheets the clock capacitance of the MN3007 is twice that of the MN3004, which you would expect from the increased stages.  However the other performance data doesn't scale up/down, making you think more is going on.   If they aren't the quite the same then that itself might explain what you see (which I believe 100%).