PWM Phaser Questions

[Eb7+9]

I wanted to build something that would allow me to investigate the properties of PWM'd-Gate resistors in real life ...
as theory dictates the followng:

Requiv = Ron/%duty

basically, a f(x)=1/x type function
and, incidentally, the exact same type function as we see in jFET VCR applications; as Vgs approaches Vgs(off)

to this end I programmed an AVR board (Arduino Pro Mini)
to give me a statically controllable OFFSET down to 0.39% duty (1/256 step)





this is well beyond what any analogue envelope-to-duty-cycle converter can do
the MXR Env Filter is what got me started in this, and it can't go much below 20%

the resistance factor will typically be quite low in any analogue driven PWM circuit
of course, the advantage there lies in its smoother (more continuous) variation in time
whereas digital drive invariably spits out values that are "stepped" discretely in time ...

well, as far as actual resistance levels go
I'm glad to report test measurements faring better than simulation
and by quite a bit ...

that was a big surprise for me

at bit 00000001 the frequency response shows a notch at 40hz (roughly)
at bit 00000010 the notch lies at 80hz (roughly)

at bit 11111110 the notch lies at 40kz (roughly)

measurements done with a DSO-Quad

seeing my circuit is comprised of cascaded all-pass filter (same as P45) using 0.01uF caps
the notch frequency can be used to estimate Requiv by equating resistance to reactance

Requiv = 1/(2piFC)

a 40hz notch implies Requiv = 400k ohm
a 40khz notch implies Requiv = 400 ohms




in other words that's a 1:1000 ratio over a 100% to 0.39% duty cycle variation
that's what I'm measuring at least ...

apparently, this would then confirm (and even somehow better) theory

successive notches move up by about 40hz each ...
so the starting value doesn't seem out of line here

---

as far as the audio phase-vibrato effect goes ... the stepping that occurs in the first few bits
causes faint but ever present noise that cannot be eliminated thru filtering
(to be expected of course)

this can be explained by the fact that the first few bits causes resistance jumps
onto the following values:

400k, 200k, 133k, 100k, 80k, ... etc corresponding to each 40hz jump in notch frequency


a bit of a bummer of course,
considering I'm not only getting super lush phasing, but the response is identical in both channels
which is not always perfectly or easily attainable in optical or jFET based approaches
(the PWM-Gate approach does away with coarse variations and consequently need for matching)

of course, having a notch going up to 40khz is totally un-necessary
and for comparison the Univibe doesn't really go far above 10k
(cf. Bode plot from my original Univibe tech page)



and so, my next tweak will be to up the 0.01u caps
to about 0.033u or 0.04u

this will bring the notch minima well below the audio range
which is ok as I mean to "waste" those first jumps,
making use of the lower range of resistance where adjacent values are close enough together ...

that's where the OFFSET control comes into play

it's only the first 5 or 6 "relative" steps that cause noise
after that I don't hear it ...

so, who knows, I might get lucky here

[amptramp]

Are you talking about the phaser from the first post here?

http://www.diystompboxes.com/smfforum/index.php?topic=76747.0

or this one from the same thread?



I find it sort of hard to follow arm-waving arguments without a schematic to look at.

[ElectricDruid]

I wanted to build something that would allow me to investigate the properties of PWM'd-Gate resistors in real life ...

Nice work! That's exactly what we needed to know.

I'd like to point out that for a PWM signal, the fact that the digital output jumps in discrete steps isn't such a big deal as it would be for other waveforms. For example, an analog ramp wave given some frequency modulation produces a curved ramp waveform. No digital waveform that only switches at the end of the period will produce exactly the same effect. But for a square wave or a PWM waveform where there are only two levels anyway, no changes in the middle of the waveform are visible until the point at which the waveform changes state. This has the effect of minimising differences between analog-modulated and digitally-modulated PWM waveforms.

More of an issue is that you're getting 1:1000 ratio in only 256 steps. That's going to sound steppy, I'd have thought. But don't forget that you can fit a parallel resistance to tweak the response further. That might help spread your 256 steps over a better range.

T.

[Eb7+9]

sorry to contradict you Tom,

but putting a fixed resistance in parallel with a stepped resistance still gives you stepped resistance
no smoothing can be had that way I'm afraid

turns out I was getting undue amounts of switching noise from the 4066 IC

I compared the 4016 and 4066 datasheets and noticed the extra stuff in the 4066 ...
which made me suspicious, an extra path for the clock to feed thru perhaps (?!)

the 4016 consists only of a pair of inverters and a pair of pass devices
nothing else ...

all my problems went away after converting to the 4016
performance is near-flawless

---

amptramp, ... I was refering to the MXR Env Filter oscillator range
specifically the PWM lower limit %

but I'm also hinting at the MXR 161 PWM phasor design
as well as the Parasite Studio phaser

for the same reasons ...
or, AFAIK any analog PWM-variable LFO design for that matter

---

before the IC swap I had changed the 0.01uF caps to 0.047uF
this was to make use of the OFFSET control to avoid the lower steps

it did lower the glitch/noise levels but didn't cure the problem completely

in so doing (cap swap) I still have a huge amount of range left at both ends
but I'm going to stick the 0.01uF back in to see if I end up getting considerably more top end chime ...

I'm currently testing with a Wurly 200 series piano, which is a little dark sounding to begin with
so, interesting to see if going back to an extended high range does anything in that context

---

the next step for me will to convert the stereo version to four-stage mono
yielding a 5v mixed-signal/PWM P90 emulator of some sort ...

and from there,

converting the 0-5v Arduino output to 0-9 and 0-18 at high slew rates
in order to experiment with larger signals and bias voltages

a very fast comparator is necessary here ...
and, a low-Z discrete version with saturation compensation is fairly easy to pull off

of course, all this to eventually build a PWM vibe and PWM stereo vibe - one of my main goals
the parametric range testing says I has a shot ...

to this end, it would be great to see the ElectricDruid code
with a similar OFFSET control embeded within

I think we talked about this once before Tom

[ElectricDruid]

sorry to contradict you Tom,

but putting a fixed resistance in parallel with a stepped resistance still gives you stepped resistance
no smoothing can be had that way I'm afraid

No worries, you're not contradicting anything I said. I only said that putting a resistor in parallel would alter the *range*, not give any smoothing. My hope was that by changing the range you might be able to make the steps less perceptible to the human ear, but that's not the same thing as getting rid of them.

After all, there's no point having (say) 10-bit PWM with 1024 steps if you then only use half of them because the others are way outside what's useful. You're losing the benefit of the extra resolution like that, and we really need all the resolution we can get.

I think we talked about this once before Tom

Most likely. A PWM phaser based around the TAPLFO chip has been on my to-do list for a long while.

Good luck with yours.

Tom

[jubal81]

Most likely. A PWM phaser based around the TAPLFO chip has been on my to-do list for a long while.

Love to see that. It'd be a real paradigm shift. Using a uC and 47-cent chip  -- with that level of performance and circuit simplicity -- would be a game-changer.

[ElectricDruid]

Most likely. A PWM phaser based around the TAPLFO chip has been on my to-do list for a long while.

Love to see that. It'd be a real paradigm shift. Using a uC and 47-cent chip  -- with that level of performance and circuit simplicity -- would be a game-changer.

Sorry, but I can't agree. It's a pretty obvious idea and it's been kicking around for *forever*. There's a ton of previous threads on here, without starting on everywhere else. Still, that doesn't mean it isn't a good idea, and it doesn't mean that it's been done well yet. But paradigm shift? Naw, not so much.

T.

[Eb7+9]

After all, there's no point having (say) 10-bit PWM with 1024 steps if you then only use half of them because the others are way outside what's useful. You're losing the benefit of the extra resolution like that, and we really need all the resolution we can get.

I think you're missing the point here ... it's all relative to a target resistance range
and the jumps that follow from the starting position

with 10bits we're now dealing with smaller resistance jumps between encoded values
when we look at it from a certain (target) resistance on ...

regardless of resolution the first two steps always involve a doubling of resistance
but after that the successive differences become smaller very quickly
obviously, the successive differences drop at a faster rate with higher resolution ...

so 10bit will produce less stepper noise than 9 bit, around a given (target) resistance level,
and 9bit less than 8bit ... etc etc

note: the target resistance relates directly to the notch location ...
and is (should be) under our control when designing phasors

so, tossing out the first five or six values (say) in the 10bit case leaves us with way finer resistance spacing soon after that
and starting at higher resistance values relative to the 8bit case ...

(we're not throwing out anything near half the values here ...)

so, in effect, being left with more noiseless range to play with in the high resistance area ...
that's what we're really looking for here, since it affects how low in frequency the notch reaches
and so extends phasing into the fundamental range (50hz to 250hz) as opposed to just phasing string harmonics

---

Tom, just for fun consider the flip side ...

at 10bit resolution we're now under 0.1% duty cycle at the minimum mark
but it also means that a 16Mhz PIC won't be able to put out a clock faster than 16khz at 10bits
your 10bit code ran at 19khz, for sake of comparison ...

to get a 40kHz clock you'd need a controller running around 4Mhz internally ...
we know they exist ...

next question, at 40khz/0.1% means a pulse width of 25nS ...
which corresponds to a 20Mhz clock (50nS period)

the datasheet for the CD4066 shows topping out at 6Mhz switching when running at 5v
and both CD4016 and CD4066 top out around 10Mhz when running at 10v

you'd need faster gate IC's than these two

or, more likely, limit ourselves to 9 bits when seeking to use these common parts
at 9 bits, the minimum duty cycle becomes 1/512 = about 0.2%

which should land somewhere around 800k ohms max if my test numbers are right,

and so first values would be 800k, 400k, 267k, 200k, 160k, 133k, ... etc

as target, let's take 20k/22k as the benchmark resistance values
(eg., the "hard" limits imposed in the P45 and P90 phasors)

notice that we get to 20k after 40 steps ...
at step 41 Requiv becomes 19.5k ... a 500ohm difference

if we were trying to emulate that range we'd be throwing away 40 out of 512 values ...
and getting low-noise phasing in the process (stepping noise range is long gone by then)

---

playing with my latest 8bit unit today and after throwing away maybe 10 steps at the most
I was still getting tons of phasing with hardly any noise

5 or 6 more steps and whisper quiet behavior, and still tons of phasing/vibrato in the fundamental ranges

if anybody ever gets a 10bit system operating somewhere between 30khz and 40khz
it would likely be the best we can do using discrete techniques

unfortunately your 10bit chip running at 19khz aliased noise
in the signal path in the TapTempo stereo unit I built two years ago

following my request, the double speed version running 9bits at 38khz and saw the clock whine disappear ...
but with stepper noise being a serious issue by lack of an OFFSET control

at the moment I'm seeing great results with 8bits encoding running at 32khz,
with the use of a proper OFFSET control

when you start experimenting for yourself you'll see that it's a necessity here ...

if you ever get that going let us know
I'd like to give your 9bit/38khz chip another go ...

[ElectricDruid]

Sorry, you're right, I misunderstood some of what you were saying. Yes, the steps aren't even, so you can dump the few worst cases and that helps a lot, and your point about the pulses getting so short at the fast end is well made too. I get it now. Thanks for bearing with me - sometimes a bit slow on the uptake

If I was doing it again, I'd use the newer "enhanced" PICs which go to 32MHz with the internal clock. Instead of the 19.5KHz PWM frequency, you can get 10-bit at 31.25KHz, which should be good enough. Failing that, you could go for 9-bit at 62.5KHz, which is certainly high enough to get rid of clock whine, but might throw up more problems by being too fast for the switches.

Tom

[Eb7+9]

If I was doing it again, I'd use the newer "enhanced" PICs which go to 32MHz with the internal clock. Instead of the 19.5KHz PWM frequency, you can get 10-bit at 31.25KHz, which should be good enough. Failing that, you could go for 9-bit at 62.5KHz, which is certainly high enough to get rid of clock whine, but might throw up more problems by being too fast for the switches.

thanks for that info Tom,

FYI, 31.44khz is what I'm getting away with ... no issues

I'm already getting great results at 8 bits
would be interesting to see on much less bottom truncation can take place when encoded at 9 and 10 bits resolution

if you ever get your code working on that 32Mhz PIC I'd like to experiment with it ...

[POTL]

Hello everyone, this is an old but interesting topic. The 4066 chip is successfully used as a variable resistor in the MXR Envelope Filter circuit. I've seen phasers circuits with this chip all over LDR or Jfets. Quite an interesting idea. Tell me, after 5 years, have there been answers to these questions? 1) How to correctly calculate the minimum and maximum resistance values 2) Does this chip have clipping problems like field effect transistors?

[amptramp]

I thought the most ideal example of a PWM phaser was this one where there is a high frequency sawtooth oscillator and a sinewave LFO and the CD4066 switches are turned on when one waveform is above the other:

[POTL]

interesting scheme Switching mode between LFO and detector, as well as mix between positive and negative feedback. However, it is not clear how to calculate the filter frequency, the capacitor values ​​are taken from phase 90, however, the limiting resistor parallel to the switch is very large, 40 times larger than the value of phase 90, this gives an understanding of the resistance at the maximum value, but what is the minimum? Will the signal be limited as with field effect transistors? Can we use a regular LFO or 4049 is needed?

[Rob Strand]

interesting scheme Switching mode between LFO and detector, as well as mix between positive and negative feedback. However, it is not clear how to calculate the filter frequency, the capacitor values ​​are taken from phase 90, however, the limiting resistor parallel to the switch is very large, 40 times larger than the value of phase 90, this gives an understanding of the resistance at the maximum value, but what is the minimum? Will the signal be limited as with field effect transistors? Can we use a regular LFO or 4049 is needed?

There's a whole heap of stuff going on.

The filter is called a switched conductance (allpass) filter.    The idea is to switch between two resistor values and the longer the time spent on one value the more the "effective" resistor looks like that value.    In the case of the posted circuit the two resistor values are:

                    Switch on:            Ron  = (47 ohm  + Rswitch)  //  1M   ; // = parallel
                    Switch off:            Roff  = 1M

                   Rswitch is resistance of the CMOS switch perhaps around 180 ohms
                   and that makes Ron  = 267 ohms.

If you switch between the two resistors the whole idea is the amount of time spent on and off can be use to adjust the effective resistor value Reff.     If you spent 50% of the time on each you might guess the effective resistance is the average of Ron and Roff that gives  Reff  = 0.5 * 267 + 0.5 * 1M  = 500k  BUT that is wrong.    You need to average the conductance G = 1  / R not the resistance, so that gives   Geff = 0.5 * (1/267) + 0.5 * (1/1M)  = 0.001877 = 1/533 and then Reff = 1 / Geff = 533 ohms.  So by spending half the time the resistance looks like about double the smaller resistor value Ron.

If you only spent 1% of the time on 1k  267 and the other 99% on 1M  you would get Geff = (1/100) * (1/267) + (99/100) (1/1M) = 38.4e-6 = 1/ 26k.  So Reff = 26k which is about 100 times larger than the smaller value Ron.   Because 267 ohm is so much smaller than 1M we find the effective resistance is largely determined by the smaller resistor value Ron.

The way the on and off time is controlled is using a PWM modulator.   There are two oscillators.   A low frequency opamp oscillator which is the LFO and a high frequency clock oscillator using the first two 4049 gates.    The clock frequency is the PWM frequency.   In order for the switch conductance filter to work the switching frequency needs to be somewhat higher than the maximum audio frequency ideally more than 5 times the audio frequency, so maybe 50kHz or 100kHz.   Since the frequency is so high we need to use a 4049 for the high frequency clock.

The PWM allows LFO voltage to change the pulse width and that controls the effective resistance.   The two oscillators are combined at the TL064 comparator (opamp) IC3C.    If you consider a 100kHz clock that is a period of 10us and if you want the Ron resistor to be on for 1% of the time that means the switch needs to be on for only (1/100)*10us = 0.1us.   That's pretty fast and the TL064 is only barely going to do it.   You can help it out by lowering the PWM clock frequency, which will impact audio quality, or you can restrict the minimum duty cycle to more than 1%.   Either way the design only just makes the audio bandwidth and range of sweep for a phaser.

[Eb7+9]

after 5 years, have there been answers to these questions? 1) How to correctly calculate the minimum and maximum resistance values 2) Does this chip have clipping problems like field effect transistors?

the theory doesn't change in time ...

Minimum resistance is obtained when switch is on all the time ... 100% duty

Maximum (equivalent) resistance when switch is open for minimum amount of time ... see my post above, there's an obvious trade off between operating frequency and average turn-on/off times of said gate ... no arm waving there

A switch has no headroom issues, it either blocks or passes current ... the whole thing relies on the mathematical basis of RMS, which is well beyond the level of ... oh, never mind

[ElectricDruid]

That schematic neatly demonstrates why using a uP to generate the LFO is such an appealing idea. At least half the circuit is just creating the PWM LFO. The bit that actually does phasing is pretty simple by comparison. Now imagine chucking all that "extra" stuff away and having one little eight pin chip with more waveforms, tap tempo, whatever else you can dream up.

[bluebunny]

Now imagine chucking all that "extra" stuff away and having one little eight pin chip with more waveforms, tap tempo, whatever else you can dream up.

Cheeky!     But true...