First-time builder, help debugging Phase 45

[santxo]

Dear all,

first post here.

I'm a born-again first-time builder (built some distortion and delay pedals about 10 years ago, now rediscovering the craft), looking to get some advice on debuggin a Phase 45 build that I did in line with frequencycentral's original layout (http://s210.photobucket.com/user/frequencycentral/media/Phase45.gif.html), but without the "univibed" mod and mix pot, but with all else as in the schematic, including the 5,1V zener. I've checked and rechecked the connections and I can't find any unwanted ones - had a few, solved those, still no effect. The issue is that there is no audible phasing effect happening.

In line with the debugging page here on the forum, this is the info that I can think of... First, the distinctions from the original design: the FETs are a pair of matched (so the specialist site claims) 2n5952s.

The voltages are as follows:

Vbat = 8,83
Vref = 3,84

IC1
1  3,86
2  3,85
3  2,11-6,71
4  0
5  3,83
6  3,84
7  3,82
8  8,80

IC2
1  3,86
2  3,84
3  3,84
4  0
5  3,37
6  3,67 - 5,67*
7  8,19
8  8,80

Q1
S  3,84
D  3,84
G  2,66 - 3,04

Q2
S  3,84
D  3,84
G  2,65 - 3,04

*These are the values of the largest span, set at an Rbias of around 75kOhm.

I've followed the transistor pinout from this page: http://www.electronica-pt.com/db/componentes.php?ref=2N5952 (bottom-up view)

Things I've tried with no avail (mostly advice found here on the forum):

1. 10k pot wired in parallel with R1 to raise Vref incrementally up to 5,56V.

2. Bypassing R24 and R25.


Any advice would be appreciated! Thanks!

[duck_arse]

hello santox, welcome and welcome back (how did you get away the first time?).

pin 7 of IC2 should be much closer to 3V8 than 8V2. find out why it isn't.

[santxo]

Hey duck_arse,

thanks for the info, and for the welcome (I was lost to grad school abroad and subsequent work there).

I've actually rechecked everything, and can't find a faulty link, but have discovered that the V on pin 7 of IC2 is actually not the stable voltage that I reported first time round, but actually changes in 3 second gaps between 1,36 and 7,85 (with a reduced Vbat from the previous measure at 8,5V). I've not touched the circuit between the two measures. I must have measured the V during one phase first time round, and the same for pin 5, which is not a stable voltage either, but changes with the same frequency as that of pin 7, between 3,26 and 5,43.

Could a faulty (?) op-amp be causing this?

[duck_arse]

could be a faulty, but why would it be? no need to expect that kind of wurst (the sausage is vrr popular hereabouts).

your Vref voltage, whatever it may turn out to be, measured at the two resistors//cap should be rock steady, not wavering, and the same at each point connected to it. so, you need to find what is making it go silly.

find us a circuit diagram to point to that matches the layout you used, to avoid confusion. power off, pull the IC(s) if it is socketed, and measure the resistances between the IC's connections on the board. measure the resistances between supply and Vbias, and ground and Vbias, and from Vbias to all those places it connects to. somewhere a number will be off, you just need to find which one it is.

it sounds like your battery is draining faster than it should, which possibly points to excess current being drawn somewhere.

also, post some pictures of what you've built, component side, solder side, and off board parts, so we can have a good look, you never know what we might/can/often do find.

[santxo]

The changes of V at pin 7 of IC2 have now been traced to the 470k pot. On one end of the scale there's the phenomenon described above (voltage steps of 1,36 and 7,85), and on the other, there's a constant voltage fluctuation between about 4,0 and 5,0V). I figured this might be how the LFO works (somehow), so I measured Vgate at both Qs, and they are indeed changing between a fluctuating range between 2,56 and 3,0V in the first case, and a stable 2,83 in the other. However, no effect is still audible. Could this then be that Vgate is too low in both cases to trigger the effect?

Here are a few images of the build. I'm only seing now that they're a bit dim, I'll retry tomorrow.

[duck_arse]

photos are bright enough, i'm just not sure what it is they show.

I can see you have knifed some, but you need to get in and clean between ALL the solders, flick all the blobs of flux off you can, and make 100% sure there is no nothings betweeen runs. same for those odd blobs topside, and the burnt-thru insulations would be better fixed.

with insulated wire links (and flying leads), you are best off running them on the component side, and poking through only to solder. this means less chance of shorts, more support for the wire.

what's the caper w/ the little board w/ transistors on?

and any sign of the circuit diagram? Vbias should be stable where it is generated, it can then have some wobble added to. the circuit dia will show us how this is done.

IC2 pin 7 must follow its inputs, yours is way off. this is not right or good. find why.