Calling DAC experts (BOSS DD-2/3)

[cd]

Alright, I've looked at this one ten ways from Sunday, but it still has me stumped.  Either that or I'm understanding it correctly, but it's some different toplogy that I've never seen (which is entirely possible, since I know virtually nothing about ADC and DAC circuits).  OK, specifically, how the ADC and DAC work in the BOSS DD-2/3.  Let's use this schematic:

http://www.8bitsindgenug.net/boss_dd2.png

The ADC is a SAR (successive approximation register) type that uses a sample and hold.  SAR info here:

http://scitec.uwichill.edu.bb/cmp/online/el21c/lesson11.html

The incoming signal, which has been compressed by IC2a, is sampled/held by the analog switches in IC4a and 4b and capacitor C41.  C41 holds a tiny amount of charge which is then fed into the 311 comparator. 

Now the comparator needs something to compare the sampled voltage to - the SAR uses a DAC to convert a binary number into an analog voltage.  This voltage is fed into the comparator and the SAR (which is inside the main controller chip) runs back and forth from the MSB to the LSB, throwing out these numbers (which are converted to voltages by the DAC) running back/forth until it finds a match for the sampled voltage.  It then stores this number in the memory chip and moves on to the next sample.

The DAC is formed by resistor ladder R73 and IC6 (the 5534 opamp) which is a vanila R-2R ladder DAC.  However as far as I can tell, the DAC that is supposed to be in the SAR, and the output DAC itself (which sends out the delayed signal) are both the same DAC??  Am I missing something here?  The DAC in the SAR is used to run the comparator, so how can it do "double duty" as the DAC for the delayed signal?  Or is the incoming input signal being compared to the delayed signal... but then wouldn't there be problems when the incoming signal is compared not to a SA of numbers but its own self 800ms before?

Bottom line, shouldn't there be TWO DACs, i.e. pin 3 of the 311 comparator should be fed by a line from the main controller chip (a DAC inside the chip) NOT the output DAC itself?

Any pointers greatly appreciated.  Or even a textbook recommendation for some basic digital circuits (like a 1st year EE course)!

[Peter Snowberg]

You have a very good understanding of how this stuff works. Good show. 

That design is made for lowest possible cost which is why the D/A ladder is being used double duty.

If you look right beyond the 5534 buffer, you'll see a couple stages of 4066 CMOS switch. When the signal is being generated for the output, the switches are closed and the input is not being sampled. When it comes time to check the input, the 4066 switches are opened and the D/A get dedicated to generating the reference comparison voltage.

The D/A useage just keeps ping-ponging back and forth at twice the sample frequency.

That is a somewhat complex circuit, because it's behavior is largely controlled by software. The lack of visibility of the software also makes it much more difficult to decode the operation, unless you have a logic analyzer.

Pretty much everything in the audio world has migrated to sigma-delta style converters because for AC signals, they're superior in every way. When it comes to DC though..... SAR is still a key player.