Analogue Delay (Using MN3007)

[edash]

Hello everyone,

I found this schematic the other day through a link from the synthdiy.com archive.

http://www.itn.liu.se/~nikro/diy/delay/index.html

Quite an interesting looking circuit, using the mn3007 and mn3101 for an analogue delay. The MN3007 only produces a 50ms delay on it's own, which is pretty small.

Would it not be in this case possible to cascade multiple chips - one after another, to produce a longer delay signal? I happen to have a rather large stock of the chips at the moment, and this could put them to good use

Many Thanks

[Mark Hammer]

Thanks for the link.     An MN3007 is capable of slapback echo for rockabilly tones but don't expect discrete echoes out of a single chip implementation.

In principle, a quartet of MN3007s is no different than an MN3005, just a bunch of FETs and caps.  Indeed, Maxon's recent analog delay uses 8 such chips for some bizarre reason.  So yes, you CAN achieve longer delay times using multiple MN3007 setups.

Note however that every BBD needs to have a DC bias voltage on its input and have its complementary outputs balanced, and that there needs to be a single clock or have multiple clocks ganged and driven by a master clock.

Generally, it is possible to use a single bias voltage source to bias up all the chips, since their individual "ideal" bias will not be too different (that doesn't stop Maxon from having individual bias trimpots for each BBD in their pedal).  A DC blocking cap goes between each consecutive BBD and the bias gets reapplied to the input of the next BBD in line. The balancing of the two complementary outputs of each chip should either be done with a trimpot or by 1% fixed resistors, rather than with 5% resistors.  Again, Maxon has seen fit to use a trimpot per BBD to fine tune the balance between outputs.  Optimal matching of complementary outputs helps to reduce noise.

Also note that should yo choose to stuff 8 of these puppies into a circuit, you will start to run into problems with the clock if all you use is an MN3101.  All the teeny capacitors in parallel across all those BBDs load down the MN3101's output and turn nice crisp square-wave clock pulses into roundish-looking things, which reduce the fidelity of the sound.  You CAN use 8 or even more such BBDs, but you will need to buffer the clock output  so that it can handle all the capacitance it sees at the other end.

[edash]

Sounds very interesting, thanks for that Mark.

I'll look into that, does anyone have the schematic for this maxon pedal, it would be interesting to look into how it's done on that. Thanks for the info on how to link the chips, what would you recommend I should use to buffer the clock signal?

Many Thanks

EDIT: Just found a post of yours on firebottle that mentions buffering the clock signal, I'll have a look at that schematic on the ampage link (http://www.firebottle.com/fireforum/fireBB.cgi?cfg=fx&forum=fxmt&read_prev=263734)

EDIT again : The anderton flanger: http://ampage.org/hammer/files/Anderflange1.PDF

[Mark Hammer]

The Maxon pedal is a new release (2005, I believe) so schematics are generally unavailable.  The pedal is a complex enough board that reverse-engineering it isa VERY tough slog, and well-built enough that no oone has likely had to order a factory schem to repair one.

In general, it appears to use the same tried and true formula of op-amp > compressor > lowpass filters > BBDs > more lowpass > expander opamp.  No great magic, really, but with 28 trimpots on board, they have aimed for precision adjustments to yield maximum quality.

[edash]

Ah, probably a little tricky for me to manage on my own then 

I'll have a poke around and see what I can work out for myself

If worst comes to the worst, how many BBDs do you think I could link without having to buffer the clock?

[Mark Hammer]

If you look at the datasheet for the MN3101, it is spec'd to drive up to 8192 stages ( = two MN3005's or eight MN3007's) "directly", though it is not clear at what clock rate.  Keep in mind that, similar to the problem of cable capacitance, the problem is not with lower frequencies but with higher ones.  If you were trying to super-clock these things to get, say, wide flanging with ultra-fidelity samping rates, then clocking 8192 stages to achieve <1msec delay would very clearly require some serious buffering.  In the context you describe, though, the goal is to keep the clocking reasonably slow so as to achieve more delay time.  Here, you can probably use an MN3101 to drive eight 1024-stage devices with minimal difficulty, just as long as you don't try to force it to be able to produce, say, 5msec delays at the short end, or something like that.

[edash]

Ok, many many thanks for that information Mark.

I'll make up the circuit and see what results I get playing with the chips

Once again, thanks for you great expertise and for taking the time to help!