Help with FET phaser low-distortion implementation

[varialbender]

One of you posted a few improvements on FET phasers, and I'm interested in trying it out, though I'm not entirely sure how to do so. I'm iffy on what to do with biasing. It might help to see a more full schematic of a phaser that uses this, though if you don't have time for that, an explanation would still help a ton. The link was:
http://www5b.biglobe.ne.jp/~houshu/synth/PhaseFet0205.GIF

Any help is much appreciated
Thanks

[George Giblet]

All you need to do is make sure the MOSFET (or JFET) source is at the nominated bias potential (ie.  Vcc/2 for single supply stuff and 0V for dual supply stuff).

In each of those ckts it's adviseable to add a resistor across the drain and source of MOSFET (or JFET) say between 10k and 1MEG, typical would be 27k to 100k or so.  That will stop any funnies with the biasing when the device is fully off.