old-days delay

[Dimitree]

hello everyone
I'm trying to get a digital delay out of old chips and logic ICs.. Someone here will say: stop! you don't need to, there are plenty of modern alternatives. Sure, but my purpose is to learn, I don't need a digital delay, I have many of them.

So here I have a schematic of a '80s digital delay
http://www.ed-sounds.com/board2.png

this is only the digital section: the input and output signals are filtered elsewhere with Emphasis and LPFs. Of course the feedback path and the mixing sections is done in analogue like every delay like this one.
The CPU that handles pots and switches is missing too..the only piece of CPU that is connected to this schematic is the 10-bit bus that supplies 4519 ICs on the center-bottom of the schematic, and another bit "PC0" that is responsible of the WE signal for the DRAM.
Last, there's a VCO input that accepts either a square wave or a triangle wave (with slighly rounded bottom), swinging from 2V(min) to 4V(max), with a maximum frequency of 16hZ.


So far what I understood is:
since the max delay is 1024ms, I think that the 10-bit bus from the CPU sets the ms time (2^10 = 1024), that all that logic under the DRAMs converts that number into address for the DRAM.
The ADC is a SAR+DAC, 12bit, and every bit is stored in 64k DRAM chip.
The VCO sets the sample rate for the conversion (acting on the Sample-Hold gates), but I don't understand what it happens when the VCO gets higher (or lower), how can the delay produce a modulation effect?
Furthermore looks like, after the S-H on the input, there's an attenuator that is engaged if the signal gets too hot, if yes, that condition gets stored in a 13th bit, and the attenuation gets boosted on the output.

It isn't clear to me how the address logic circuitry and the VCO circuitry are working togheter..and why is needed all that circuitry to set the address for the DRAMs..
can anyone help me understand?
many thanks
Dimitri