runoffgroove JFET Vp measurement mod

Started by gaussmarkov, January 31, 2008, 08:23:37 PM

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George Giblet

> i was focussed on capacitor leakage, not knowing that JFETs have leakiage also.  having just looked at a datasheet,
Ah that's what is going on!  Yes, I'm thinking JFET leakage, which would make the cap based measurement produce high Vp's.  What you said about cap leakage is correct, the JFET would conduct current to match the cap leakage and the Vp produced would, for all practical purposes, still be close to correct.

>if that is successfull then i will give some thought to fitting the curves. you don't happen to have a reference on how to do that do you?  icon_biggrin

I used to write program which use complicated optimization mathematics.  These days I tend to use Excel's solver feature.  See this site for an example. 

http://www.analogservices.com/excel.htm

At some point you have to enter in the model equations that descibe the JFET into excel.    There are many pitfalls to this stuff.  You have to be very sceptical about the numbers produced.  The main advice I can give you is: 
- Always try different initial guesses for the parameters and see if you end-up with similar results.  Try to use values close to what you expect, but try values say 1.5 to 2 times the expected values as a test.
- Try to scale the optimized parameters around  0.1 to 10.  For example Vp, which is around 0.5 to 5V, and Idss is 10mA = 10e-3. Rather than get get optimizer to find the small Idss value create a new variable which is the mA version of Idss then create another column/row of the actual Idss which is 1e-3 times the mA version.  The equations then use the actual Idss.  It's not such a big deal with Idss because it's not too much different to 1 but if you are optimizing caps which are 1nF = 1e-9 the optimizer often produces rubbish.


> also, i have gone ahead with designing an 4-stage phaser that might accomodate JFETs with different Vp values.

It wil be interesting to see how it goes.  I think matching the Vgs=Vp cut-off point is *the* most important thing to do.  If you get that right the mismatch in the sweep range is close to inaudible - I've done controlled tests using DSP's to model the mismatch.  If you used widely mismatch JFETs like a J201 and a 2N5457 you might be able to hear something, but it won't sound bad!


gaussmarkov

Quote from: George Giblet on February 09, 2008, 08:11:12 PM
>if that is successfull then i will give some thought to fitting the curves. you don't happen to have a reference on how to do that do you?  icon_biggrin

I used to write program which use complicated optimization mathematics.  These days I tend to use Excel's solver feature.  See this site for an example. 

http://www.analogservices.com/excel.htm

At some point you have to enter in the model equations that descibe the JFET into excel.    There are many pitfalls to this stuff.  You have to be very sceptical about the numbers produced.  The main advice I can give you is: 
- Always try different initial guesses for the parameters and see if you end-up with similar results.  Try to use values close to what you expect, but try values say 1.5 to 2 times the expected values as a test.
- Try to scale the optimized parameters around  0.1 to 10.  For example Vp, which is around 0.5 to 5V, and Idss is 10mA = 10e-3. Rather than get get optimizer to find the small Idss value create a new variable which is the mA version of Idss then create another column/row of the actual Idss which is 1e-3 times the mA version.  The equations then use the actual Idss.  It's not such a big deal with Idss because it's not too much different to 1 but if you are optimizing caps which are 1nF = 1e-9 the optimizer often produces rubbish.

as it happens, i have some expertise in this area.  this is all good advice.

what i need now is equations that work well in the neighborhood of Vgs=Vp.  i'll start poking around.

i just graphed Ids versus Vds for Vgs=0 for one of those JFETs.  so cool.  the quadratic relationship for Vds<-Vp is just stunningly accurate.  i fit it in excel, too.  :icon_wink:  i'm really impressed with how well the simplest theory works for that case.  it forecasts an Idss that is slightly too high.   :icon_cool:

Quote from: George Giblet on February 09, 2008, 08:11:12 PM
> also, i have gone ahead with designing an 4-stage phaser that might accomodate JFETs with different Vp values.

It wil be interesting to see how it goes.  I think matching the Vgs=Vp cut-off point is *the* most important thing to do.  If you get that right the mismatch in the sweep range is close to inaudible - I've done controlled tests using DSP's to model the mismatch.  If you used widely mismatch JFETs like a J201 and a 2N5457 you might be able to hear something, but it won't sound bad!

that's just what i want to hear! :icon_biggrin:

thanks!!!