JFET bias calculations

[demonstar]

I think after trawling through and through past posts here and articles elsewhere I am well on my way to understanding this but I've come a bit stuck piecing it all together. I was hoping maybe you guys could give me a hand? Here goes...

I have a JFET that is setup in a common source configuration as follows... it has a source resistor (R_S), a drain resistor (R_D) and a gate resistor (R_G). The drain resistor is 1M which I gather to be standard (believe this is chosen for a suitably high impedance whilst low enough to prevent oscillations).

In this set up I understand that the gate resistor is attaching the gate to ground making V_G zero. This then means as V_CC causes I_D to flow through R_S a voltage is developed across R_S equal to V_S=I_DR_S. This then means as the gate is being held at zero volts, V_S is now above V_G. So V_G is negative. This means I_D is being restricted by the negative V_GS. This means I_D is now set. Now we would have to apportion the drain resistors size depending on desired output impedance, the stages gain and headroom. For equal headroom R_D+R_S=4.5/I_D because that would set V_DS to 4.5V, right?

How does that sound? What I'd like to know is how do I actually calculate the bias point? I think I am armed with the equations and the verbal explanation just can't piece the two together.

Does a JFET have a V_GS(TH) like a MOSFET or like the the bipolar diode drop that needs accounting for?The equations I believe I'd need are...
R_D+R_S=4.5/I_D
R_D=(4.5/I_D)-R_S
V_GS=V_G-V_S but since V_G=0 then V_GS=-V_S
A_v=R_D/R_S
V_S=I_D*R_S
V_D=I_D*R_D
A_v=v_out/v_in so A_v=v_d/v_g

Thanks!

[R.G.]

The reason you haven't seen a simple explanation of this is that there isn't a good, simple one. Well, there may be one, but I've never found it. 

JFETs do not have a Vth in the sense that MOSFETs do. Well, OK, they do, but it's negative. JFETs can't simply be biased by the emitter/source-follows-the-base/gate method because the turn on/off range on the gate is so large. The exceptions are the few JFETs like the J201s which have a Vgsoff of only less than a fraction of a volt. That could be coped with, but then the range of full-off to full-on varies by 3:1 to as much as 5:1.

There are graphical methods for achieving a reasonably small solution to biasing JFETs. Vishay/Siliconix had one it published, and no doubt someone has the link. I read it, didn't find it much use so I didn't bother to remember it in detail.

[demonstar]

Thanks R.G.

The reason you haven't seen a simple explanation of this is that there isn't a good, simple one

Guess that makes you the bringer of bad news today. 

There are graphical methods for achieving a reasonably small solution to biasing JFETs. Vishay/Siliconix had one it published, and no doubt someone has the link. I read it, didn't find it much use so I didn't bother to remember it in detail.

I think I may have seen that. I have certainly read articles on the graphical method. I don't really like the graphical stuff because I think quite often in the very small currents and voltages we operate at it can be very hard to read off the graphs reliably.

You mention that there isn't a simple explanation well how not so simple is the not so simple version?
Is it worth learning or should I consider JFETs an art not a science? What I'm saying is the not so simple method in reach of an AS-level student?

Thankyou!

[brett]

The drain resistor is 1M

That should be Gate resistor.  Yes?

The application note that RG mentions is educational, but doesn't spend much time discussing the "self-biasing" systems that we use here.  It spend lots of time on things like "Vref" systems where a fixed bias is applied to the gate.

Good luck with your quest.

[demonstar]

Yeah Brett thanks. Just made a typo. I'm going to try and seek that text out and read it. I've got a transistor principles book by Amos coping from ebay so I'm hoping that might have some info. on this subject in.

[brett]

3 handy JFET articles, especially wrt biasing:
Siliconix AN102 - biasing JFETs
FET principles and circuits, Parts 1 to 4, by Ray Marston.  Nuts and Volts Magazine, 2000.
JFETs: the new frontier, Part 1 by Erno Borbely.  Audio Electronics 5/1999.

All of these are available on-line.
cheers

[demonstar]

I just wanted to say thankyou folks for pointing me in the right direction and helpping me out. I couldn't find the nuts and volts article but apart from that I found the other two. The Erno Borbely article was particularly good. It has really helped. There were a couple of things such as THD that I have never heard of and don't understand but apart from that it was great.

I'm hoping a 'Principles or Transistor Circuits', by S.W. Amos that I am waiting for in the post that should come soon will be good!   

[brett]

THD = total harmonic distortion.  Hi-fi people want to reduce it to zero, but we guitarists want it in certain amounts and flavours. (ie where would AC/DC be without lots of it?)

As for the thanks.... what goes around comes around, so it's a pleasure.