AMZ booster/Mu booster 3.3uF cap -WHY?

[brett]

Hi.
I'm trying to work out why there's that 3.3uF NP cap in the middle of this circuit.
OK, I see a need for a cap in there.  As I understand it, the signal gets passed from the drain of the "bottom"/"amplifier" FET to the gate of the "load" FET.  But since the input impedence at the gate is 1 meg, why use a relatively massive 3.3uF cap?  The lower JFET has the same impedence and a much smaller 0.05uF cap on its gate.  So why is it a 3.3uF, not a 0.05uF??
Would somebody explain??
I'm fully ready to be embarassed! :wink:
thanks.

[petemoore]

Maybe the amp circuit generates content that creates 'character' in a freq range that would be cut by a smaller cap. Smaller caps = different response.

[Johan]

..If I remember correctly..( its a long time ago now..) ..that simply was what Jack had in his parts-bin...but I could be wrong..anyway...He is still around, maby hi will see this thread and answer himself..

Johan

[Stevo]

The original original original version only used all .1uf caps everywhere that was in I think 1999... He has change many things since than... I know that if you cascade two with all .1uf and use J201 you will have extreme gain but an oscillation problem... You will need to use only j201 on the bottom two and MPF 102 on the top I think(say again think) will give good results...build one with all .1uf caps single only one and you will have a nice sounding unit....I was thinking that many have had this oscillation with J201 and Jack was thinking smartly looking for a pull down somewhere in the circuit..I dont know but Jack may chime in if he does you are lucky he is a smart technician .. a great help in a circuit I did with a booster and the Harmonic Percolater..

[Transmogrifox]

The stability issue certainly makes sense.

[puretube]

PSRR...

[brett]

Thanks for the contributions.
But they raise 2 more questions:
1.  If stability is increased.  How/why?  Does a 3.3uF electro pass less radio frequency than a smaller greencap? (I think I should know this already)
2.  I'm not sure how the power supply noise rejection ratio (the PSRR mentioned above) is improved by this cap, except maybe at radio frequencies as discussed above.  
For low frequencies, the 100 ohm resistor and 100uF cap on the supply line would certainly provide a great PSRR.

I'm a bit of a dill. :oops:
thanks for any more advice

[puretube]

look at R2/R3 and C2 here:
see 1st PIC...
like you look @ the Ub/2 biasing of an opamp...

when I compare that "miniboo" with these:
http://www.tubecad.com/may2000/,
I come to the conclusion,
that it isn`t a "SRPP", but that Q1 is rather a constant-current-source (virtually large) drain-resistor...

:?:

or maybe I`m just miising a dedicated RD & RS on any/both Q1/2,
or at least a series-R from the divider`s node to the upper grid... ?

or maybe that wedding-party last night lasted too long???
:lol:

[mojotron]

In R. G. Keen's article "Foolin' with FETs"

http://www.geofex.com/Article_Folders/foolwfets/foolwfets.htm

RG explains that this cap couples the input signal to the upper FET, such that when the lower FET pushed the signal in one direction or the other, the upper FET will then pull the signal in the complimentry direction. This is sortof a push-pull circuit.

RG States:

The entire trick to understanding this circuit is in noticing that the gain comes only from the bottom JFET. The upper JFET is merely acting as a source follower to pull up the output when the bottom JFET lets it rise. True, it's an odd source follower because the input is the voltage on its own source, but that is the way it works. (Copyright 2000 R.G. Keen)

RG starts this article stating "Get out the simulator..." That is a really good resource for seeing how this works.

[amz-fx]

But since the input impedence at the gate is 1 meg, why use a relatively massive 3.3uF cap?

The impedance at the upper gate is 500k....  and the capacitor is 3.3uF non-polar because that was what I had in my parts bin that was non-polar on the day that I made the prototype...  it has always been 3.3 since I first posted the schematic in 1995.  

Best regards, Jack

[Stevo]

Hello I have a scheme dated 1995 that I scanned in 1999 and you used all .1uf in that scheme... :oops: I dont mean to argue but what is the best interest of the circuit cap to use... I have done quite a few of these and use all .1uf and than worry about tone at the end with no problem...Would you suggest the 3.3 or like in the Shaka 5 you used a .01uf in that position..You have been a hit Jack with this circuit you should be damn proud of all the people and Fulltone who uses it and really..  Thanks for all the help over the years..

[puretube]

... ?

or maybe that wedding-party last night lasted too long???
:lol:

Yes: don`t go playing/dancing until 4 in the morning
without getting enough sleep afterwards...  

[Doug_H]

Hello I have a scheme dated 1995 that I scanned in 1999 and you used all .1uf in that scheme... :oops: I dont mean to argue but what is the best interest of the circuit cap to use... I have done quite a few of these and use all .1uf and than worry about tone at the end with no problem...

Breadboard it up and test with different value caps and see what value you prefer. What sounds good depends on the overall circuit you are using it in, guitar pickups, amp, your preferences, etc. Always let your ears be the judge.

Doug

[puretube]

app-notez?

[johngreene]

app-notez?

Nice find!

[ClinchFX]

But since the input impedence at the gate is 1 meg,

Not that it will have any real effect on the value of C2, but the impedance (with respect to ground) at the gate of Q1 is effectively 500K, the parallel combination of R2 and R3.  This is not necessarily what C2 is seeing, because C2 is not directly referenced to ground.

Peter.

[alanlan]

Jack gave the real answer to the question but it's worth adding the following:

Q1 is acting as a pretty stiff AC current source.  It has an impedance of in the 10's to 100's of K.  You could replace it with a resistor of an equivalent value but the problem is that the DC drain current is in the order of 1mA or so (roughly) so such a resistor would drop 10's of volts i.e. you'd need a much higher supply voltage.  So Q1 is acting as a very high impedance for signals while dropping only a few volts for DC bias current allowing the output to be biased somewhere near mid supply.

The amplifier is called a mu-amp because the equation describing the gain is as follows:

vo = -μ . vi / 2

μ = gm . rd where gm is the transconductance and rd is the dynamic drain resistance i.e. small signal AC drain resistance.  rd can be roughly deduced by taking the slope of the curves on the output characteristic of the device.  gm can be deduced by taking the slope of the transfer characteristic or taken from the values given.  μ is typically in the hundreds.

See here:
http://www.fairchildsemi.com/ds/J2/J201.pdf

However, the equation above does not take into account the effect of C2 (the 3.3uF).  The following equation also takes this into account:

vo = -μ . vi  . (1 + sT1)
        ---------------------
        (μ +2) . (1 + sT2)

where T1 time constant = C3 . 500K (the AC impedance of the bias network)

and T2 = 2 . T1 / (μ + 2)

What this means is that there is a low frequency shelf thing going on here. 

The gain will start to rise from the low frequency gain at a frequency given by 1 / (2 . π . T1) and then level off at the maximum gain of the circuit at a frequency of 1 / (2 . π . T2).

Put simply, it is intuitive to think that the high gain will start to roll off at lower frequencies given by 1 / (2 . π . C3 . 500K) = 0.1Hz but in fact it is higher than this by a factor of (μ + 2) / 2 which is quite a large factor.

Assuming we used a 100nF for C3 and μ = 200.  Then the gain will start to fall off towards lower frequencies with a corner at about:

320Hz (if my calculations are right).

There are a couple of other things to say:
1) you can trade off a smaller C3 with larger bias resistors but noise may become a problem.
2) this circuit has a very large output impedance and if you want to conserve the high gain, you'd do well to buffer it with a FET source follower or (high gain NPN) emitter follower.  The 100K volume shown in Jack's circuit will shunt the potential gain to a certain extent, but then again if it sounds great that's not an issue.


I hope this goes some way to clearing this mystery up a bit.  If anyone is interested enough to want the derivation of the equations then please pm me and I'll be only too happy to help.

[puretube]

app-notez?

Nice find!

Mitchell, et.al.: High gain field-effect transistor-loaded amplifier (1964...)
Artzt
which node?
USSR
amz-mb
vishay about FETs
AN-32...
http://www.diystompboxes.com/smfforum/index.php?topic=421.0
neo-Russ
thinfilm
multi-load
Blitz
Fredrick
Anderson