jfet biasing question

[darron]

i'm prototyping a circuit and at the end i decided i needed a jfet buffer. i originally had a j201 in there but they are not easily available at the major australian suppliers so i've substituted it for a MPF106/2N5485. first up i noticed that it doesn't need the half-voltage bias reference to turn on. i'm using a voltage divider to bias the jfet hooked up by a 2m2 resistor. NOW... right before the bias resistor there's a 470k resistor to ground which i need there for the a LFO/LDR volume control before it.

previously i had just used a 470k resistor to bias the jfet and eliminated the 470k resistor to ground for the LFO/LDR volume control. the bias resistor was giving the path to ground and it worked well too.

i'm wondering if there's any advantage to either setup? would the 2m2 bias resistor not have any help when there's a direct 470k resistor to ground anyway? would it be best to just use the single resistor to do both jobs? i'm expecting a knowledgeable answer will help me understand the matter a bit better, knowing which of my manners of thinking is right or wrong.


if i didn't describe it well i can make a schematic....

thanks heaps (: looking forward to a response.

[alanlan]

As long as
a) the DC conditions are correct for your required bias and
b) you don't require such a high input impedance looking into the JFET stage,

then there is absolutely no need for such a high value bias resistor.  Also, if your previous stage output is at a convenient DC level, then you can use this to bias your JFET directly without an extra bias network.

It would be nice to see a circuit though just to confirm that I've visualised it correctly.

[brett]

Hi
sounds like the 470k and 2M2 would be in parallel.  So just use the 470k.
If you are grounding the gate through a 470k pot, make sure there is no DC on the pot.  Because DC on pots makes them "scratch" when adjusted, and will mess with the bias on your JFET.
Remember, the source resistor is the mechanism for getting an upward swing on the drain of the JFET, so don't use too small a resistance value.  Sometimes I see 15k on the drain and 2 to 2.4k on the source.  I often find that values like 6.8k on the drain and 2.4k on the source work well.  Lower gain, but usually better bias and only half the output impedance.
cheers

[darron]

thanks for your responses guys. sorry about the delay to draw a picture. yes they are indeed in parallel. the variable resistor is not a pot luckily so it doesn't scratch.


i believe configuration 1 would be best, or am i wrong?

[darron]

edit: ohh.. and by best configuration i don't mean in terms of part count and convenience, i mean what would actually be better. with the 2m2 and the 470k in parallel i would think it would give a lower input impedance? i'm making my pcb layout right now around configuration 1


alanlan, what exactly do you mean by the DC conditions being correct? is there something that i might be missing?

[alanlan]

Hi,
all I mean is view the circuit with all the caps open circuit and that will leave you with the dc conditions.
Configuration 1 is better assuming you are using a 470K to provide a potential divider with the LDR.  In configuration 2, your DC bias (Vr) will be divided by the 2M2 and 470K i.e. (470K/(2M2+470K)) * Vr so Vr will not in fact be value you intended if you catch my drift.

Make sure that whatever is providing Vr is coupled to ground with a cap i.e. you want Vr to look like 0V at signal frequencies so you achieve the potential divider effect you want.

[fairfield]

Hey,

Maybe I missed something here but N-channel JFETs need a negative gate voltage with respect to the source to be correctly biased. In a self-biased configuration like this one, the bias comes from the current flowing through the source resistor, giving a positive voltage at the source with respect to the gate.

My suggestion is to use Configuration 2 but remove the 2M2 resistor going to Vr. The 3K3 source resistor might have to be adjusted to suit the JEFT's characteristics. The input impedance would be 470K + whatever value the LDR is at.

Let us know how it goes.

[alanlan]

Maybe I missed something here...

You're correct, you do need a negative voltage across VGS.  In this case the FET is acting as a source follower so you want the source to be around mid supply for a decent symmetrical headroom - this requires the gate to be raised above ground for most JFETs we use i.e. with smaller VGS ranges.  It is very dependent on the actual device though, so you either have to be prepared to tweak the bias voltage or use a scheme to work for the spread of characteristics defined in the datasheet.

[fairfield]

There is no need to bias the source and the gate.

What you're saying is true for a common source configuration, where maximum voltage swing is obtained by setting drain voltage around mid supply. But in the case of a source follower, where the gain is less than 1, the headroom is limited only by Vgs(off). This means that if the Vgs(off) of the part is 1V, you leave the gate at 0V and set the source at ~0.5V for maximum headroom.

No matter what you do, the amplifier will not pass more than 1Vac without clipping because of the 2 limits imposed; 0V and Vgs(off).

[darron]

thanks for jumping in with your input fairfield. my source for info was from here: http://www.muzique.com/lab/buffers.htm

he starts off with only a 1m resistor to ground as bias but explains that clipping begins earlier once the signal exceeds the gate-source forward voltage plus the bias voltage. in the next schematic he then adds the Vr reference, which is where i took it from. a lot of people use that info and i guess i just assumed it would be good.

i've got pretty hot neodymium pickups so i suppose i'll have to test both out and see which one works better. a preamp in the front might be a good idea to give it some more kick and see which clips first.

cool bananas (:

[alanlan]

There is no need to bias the source and the gate.

What you're saying is true for a common source configuration, where maximum voltage swing is obtained by setting drain voltage around mid supply. But in the case of a source follower, where the gain is less than 1, the headroom is limited only by Vgs(off). This means that if the Vgs(off) of the part is 1V, you leave the gate at 0V and set the source at ~0.5V for maximum headroom.

No matter what you do, the amplifier will not pass more than 1Vac without clipping because of the 2 limits imposed; 0V and Vgs(off).

You're forgetting the action of negative feedback (or source degenerative feedback as some prefer to say but lets not get into that argument).
The DC biasing sets the quiescent point on the VGS curve, but negative feedback provided by Rs limits the AC signal voltage vgs.  The more negative feedback you impose i.e. the higher you set Rs, the smaller vgs becomes.  Obviously though, you need to ensure enough DC operating current to allow the stage to drive the required load on the other side of the output coupling capacitor at full swing.

Try simulating it or building it - you'll see 

[fairfield]

Your right alanlan, my bad. I built it this morning and was turning in circles trying to figure out why I wasn't seeing the positive clipping as I turned the gate voltage beyond Vgs(off).

Bah...  I finally realized that Vgs was never beyond Vgs(off) because they were both(g and s) moving in the same direction.

Then it got me thinking about the sweet sound of a JFET's asymmetrical clippage.

[darron]

cool bananas. i've made the layout with configuration A. B did work also, which i noticed earlier on. thanks for your help guys! should go well, can't wait.