JFET sanity check

[decc]

The concept is simple, and yet I still get the on/off voltage level/polarity confused with these. Here's a simple mute circuit and how I think it works:



The R is a pull-up and the C is used to debounce the mechanical switch. I'm not sure what the diode is for, but I see it in examples so I put it here hoping someone would enlighten me.

P-Channel as shown.
The datasheet for the p-channel J177 has a Vgs(off) of +0.8V to +2.5V. Therefore worst case would be non-conducting at Vgs > +2.5V, and conducting at Vgs < +0.8V.

In the default "mute off" state the gate is pulled up to 9V and the source is at 4.5V. This gives a Vgs of +4.5V. This is higher than +2.5V so the JFET will not conduct and the signal will be unaffected.

In the "mute on" state the gate is grounded and so Vgs is -4.5V. This is less than +0.8V so the JFET will conduct, shorting the signal to Vref and muting it.

N-Channel version with J113 for opposite effect
The J113 datasheet has Vgs(off) of -0.5V to -3.0V. So worst case it would be non-conducting at Vgs < -3.0V and conducting at Vgs > -0.5.

Switch open: Vgs = +4.5V, which is greater than -0.5V. The JFET conducts.
Switch closed: Vgs = -4.5V, which is less than -3.0V. The JFET does not conduct.


Correct interpretation?