Questions about the technology of BBD Chorus Effects

[Top Top]

I have a MN3007 and 3006 that I salvaged from an old "surround sound" home theater effect that I found in a junk store.

I just finally got around to taking the chips off the old board and now am interested in what I can do with them.

I am not up for doing a huge project with them because chorus isn't really my bag in the first place, but I am interested in trying some stuff out on the breadboard and seeing if anything is worth boxing up.

Couple questions though.

When I look at the datasheet for both the MN3007 and MN3006 the example circuits are basically a couple opamps at the front (buffer/preamp?) then fed into the BBD chip, with a clocking chip to set the delay time, then a feedback control (I think) with an opamp  and then an output buffer.

So...

1) Mainly, I am wondering, what types of clock sources are acceptable? Can I make a clock from a CMOS chip rather than the 3101?

2) why is there two outputs on the 3007?

3) why is the clock input two pins?

4) Also, I think it is possible with a virtual ref, but it could be adopted to run on a single rail supply, right?

Also, anyone willing to elaborate on what they see here, go ahead:

[cpm]

get the SAD1024 datasheet, there is explained better how the BBD works
and seach for mark hammer's post about bbd's...

[teemuk]

The OpAmps at the input and output are not for buffering. They are low-pass filters and needed (in output) to reduce the HF noise inherent to BBD's operation (afterall, it is a switching device operating at a high frequency) as well as (in input) to reduce the aliasing errors/distortion that a BBD would create at higher frequencies.

The clock input is two pins because the clock signal is actually two signals with opposing phases. In other words, the other signal is simply inverted. Such trick can easily double the speed of operation because the BBD chip can now receive both high and low clock signals at the same time and use them accordingly.

Also, anyone willing to elaborate on what they see here, go ahead:

Looks like a very simple setup for BBD echo circuit: The signal passes through two low-pass filtering stages, then through the BBD that is driven by a fixed clock frequency. Finally, the output signal from the BBD is again low-pass filtered. The output has a parallel path that feeds the output signal back to input (echo control and the following buffer/amp) thus creating a repeating echo effect. The BBD, it's clock pulse driver IC and the low-pass filtering OpAmps are powered by a single supply.

[Mark Hammer]

1) Mainly, I am wondering, what types of clock sources are acceptable? Can I make a clock from a CMOS chip rather than the 3101?
Yes, although the 3101 does an awful lot of work for you in a small footprint.  Where specific clock circuits start to make a difference is where the clock frequency needs to be quite high to accomplish whatever it is you intend to accomplish.  ALL BBD chips pose a certain amount of capacitance on the clock input pins (this is almost always specified in the datasheets).  Just like capacitance in guitar cables, clock input capacitance can erode the high frequency response of whatever you feed them.  Inthis case, the clock input capacitance has the effect of turn what starts out to be square clock pulses into something more triangular or sinusoidal, providing a brief period where they are neither "on" nor "off".  Just like in the case of guitar cables, if the clock lines are buffered, the high frequency response is protected.  The specs you generally see for Matsushita BBDs assume you will be using 3101 chips, which do not provide sufficient buffering.  This is why the matsushita chips seem to be only spec'd to be clocked as high as 100khz.  If a design inteneds to clock any higher, it often resorts to a CMOS-based clock circuit and not a 3101.

2) why is there two outputs on the 3007?  See #3 below.

3) why is the clock input two pins?
BBDs function by taking a snapshot of the voltage the signal happens to be at, at any given moment, and store it as a DC voltage (an instantaneous snapshot of AC is undifferentiable from DC).  It then gets moved along from one storage cell to another.  The clock pulse tells the BBD to both take a sample, and move the sample along one step.  Not unlike the way that a RAM chip requires multiple pulses to tell it to do a succession of steps, a BBD requires two pulses to accomplish what it needs to do.  Think of these pulses as "tick" and "tock".  Because there would be no audio output during those "tick" steps when the sample is being taken, the chip is arranged in two parallel series of cells.  When one is taking a sample, the other is moving its stored samples over a cell.  Then they switch.  In this way, there is a continuous stream of interleaved samples being fed to the outputs, without interruption.  When the two streams of samples are combined in equal proportion, you get a seamless flow of samples.  So, the two complementary clock signals are used to provide this complementary "stepping" signal for the BBD.

The one noteworthy exception to this are a series of chips that Reticon produced which took in a single clock (at double the needed frequency), and did the complementary clock generation onboard.  This is why it is so difficult to replace an 8-pin SAD512D with another chip.  The 512D does this one-phase-into-two-phase trick and would require not only another BBD to replace it, but support circuitry to produce the two-phase clock.  Few pedals are able to accommodate such a plug-in retrofit.  You could certainly make a daughterboard with all the right guts to plug into where an SAD512D used to be.  But would it be able to clear all the other possible components (like electrolytic caps) sitting anywhere within a given radius of the SAD512D and still fit into the chassis?  Obviously, the potential hurdles are so great, and market so tiny, that nobody is likely to attempt to produce such a board.