Buffer Sine output from 8038

[Chugs]

I am messing around with a 8038 on the breadboard and have buffered the Sine output with an opamp. I followed the data sheet example but adapted for single supply 9V operation. Question: Can I replace the opamp buffer with a transistor like so?

[antonis]

Of course you can do it but single resistor base bias isn't the most appropriate method..
(Collector/Emitter current is strongly depended on individual transistor current gain (β or h_FE) so you can't have a "steady" bias point..)
On ther other hand, voltage divider base bias method is a compromise of resistor values and input impedance, so boot-strapping is the one-way solution for BJT buffer with high impedance..
(if you want to mess with that, we could post some shematics..)

A JFET Source follower, biased with a 1M (or higher) resistor from Gate to GND should be a more proper buffer..
(higher input impedance depended only on bias resistor value..)

In both cases (JFET & BJT single resistor bias), you should know specific transistor parameters (β for BJT and g_m for JFET) to properly set Emitter/Source resistor..
Source resistor value doesn't affect buffer's output impedance (but affects Source bias voltage, hence signal swing) whereas Emitter resistor value affects both output impedance and Emitter bias voltage..

P.S.1
Your BJT bias values are out of reality.. 
(for a current gain of 100, Emitter should stand at 38Volts - 1k Emitter resistor should be much closer to your need)
Also, IMHO, you better base bias it from +9V with a double resistor value to keep input impedance reratively high..

P.S.2
I don't know anything about output impedance or current capability of your function generator so I presume you've verified the need for a buffer.. 

[Chugs]

Thanks for the reply.

The datasheet recommend buffering the Sine output.

100K was the suggested impedance for buffer from the datatsheet so I started with that.

https://www.intersil.com/content/dam/Intersil/documents/icl8/icl8038.pdf

I will try a jfet instead.

[antonis]

The datasheet recommend buffering the Sine output.
100K was the suggested impedance for buffer from the datatsheet so I started with that.

Good start but "suggested" impedance is often the minimum one (within margins, of course) so higher than that shouldn't cause no harm..
(in your case, it should "load" less 8038 output so you'll have more "ideal" sine waveform and also more acute corners on square, triangular & sawtooth waveforms - in case of using them too..)

[PRR]

The app-notes show a coupling cap from 8038 to buffer. You surely also want a coupling cap to the output, since it sits at half-supply DC voltage, which is rude to some inputs you may want to feed.

I'd also consider an attenuator, because the 8038's output may be larger than most inputs take cleanly.

[Chugs]

So I have this version with the opamp hooked up to an opto on the breadboard and it is working. (The opt is hooked into a Lune style audio section.) If I want to replicate it with a jfet can I do it like this?

Is it better the bias the Jfet to VB or ground as Antonis suggested?

PPR, will I need cap before the Jfet base?



The Sine wave output level seems fine but if I take the output from the Square wave output that definitely needs to be padded down.

[Kipper4]

I'd try C4 before Q2 gate. Otherwise theres no DC to the led no?

Maybe as PPR Suggests put a volume style pot before the buffer too. to pad the hard signals down.
wave gen (pin2) to C4 to lug 3 of pot.
Lug  2 to Q2 gate
Lug 1 to Gnd (maybe even Vb)

For more possibilitys try a series pot wired as a variable resistor after R8, say 5k-100k