Skyripper buffer question.

[digi2t]

Hi all,

I've been mucking about with the Skyripper circuit (again), and I was looking at the buffer end of things. I've been looking at various buffer circuits, but I'm stumped as to why there are 10uF caps coming in, and going out of, the dual gang cross-fader (before the tranny).



There is also one on the emitter side of the tranny, but this one is part of the buffer, as I understand it from the circuits I've seen so far on AMZ and Beavis Audio.

Is this to prevent any pot noise (DC on wiper) from occuring, or is there an intrinsic value to the circuit here? Do I keep these 2 caps, and sub a buffer thereafter?

I've been contemplating sub'ing an opamp buffer in here, except those 2 caps have me balking here.

Cheers,
Dino

[joegagan]

those were normal dc blocking caps in normal locations, i simply chose 10 uf to maintain the low end to be messed with further down the line.

[digi2t]

Thanks, once again, Joe. I had a feeling that's what they were, but I'm still too much of a noob to be sure. And, as my old man would always say, "You don't ask, you'll never know".

I'm still working on a silicon NPN Skyripper version, but I figured the other day that if I was going to change something, I might as well go whole hog! So far, I've got the Axis Face in the fuzz section, the Omega booster penciled into the middle, and I think I'm going to try the buffer circuit from the Klon.

I figured this should keep me busy for the next ... ohhh say 40 years or so  . Besides, I might learn a thing or two in the process.

Cheers,
Dino

[PRR]

The DC voltages must be zero at output, zero on pot terminals, should be near-zero at input, but are 5V or 6V at transistor.

Caps are needed.

If you assume source has zero DC, or that pot-scratch is not a problem, then the first cap "could" be omitted. Since the real world is full of odd stuff, I'd have a cap there.

10uFd does seem generous relative to 1Meg pots. The worst-case load is maybe 100K. 0.1uFd caps might be ample: -3dB at 17Hz, -1dB at 34Hz, infinitesimally down at 82Hz even with several R-C in cascade. However 0.1uFd is a fairly large film-cap, 10uFd is a very small cheap electrolytic.

If you are replacing the buffer:

First, note that this plan is drawn for positive ground. Many plans are powered negative ground. Using electrolytics, you need to re-consider your cap polarities.

Look at DC levels on your proposed buffer. Some JFET buffers bias the Gate to ground. Then the "base" cap is not strictly needed. However many JFET, and about all MOSFET and BJT, and most single-battery opamps, require some non-zero DC at their inputs and outputs.

[digi2t]

Thanks PRR.

I'm fully aware of the polarity issue, and as I mentioned before, my project will be NPN so negative ground all around. That's been already taken care of. Thanks for the heads up though. I only used the image because I had it handy, my schematic is hand drawn (messy), and my issue was with the caps.

I'm going to be trying an op-amp buffer here, so I really appreciate your input. At the very least, I've made room for them on the vero, so I can fool around with it.
God, so much to learn, and so little time!

Cheers,
Dino