Locked in a Phase or How is it done? Syncing a pedal to an external LFO

[boogietone]

The newest iteration of my adventure with tremolo circuits has me wanting to sync with an external LFO. The practical purpose being to synchronize for recording studio use. The more esoteric reason is to better understand the circuit. The approach that I am looking at is to couple the external LFO to the trem circuit with a phase locked loop (PLL) which filtered voltage output controls a resistance in the trem's LFO circuit, via a JFET in the ohmic region, for instance. I have a pretty clear understanding of the workings and math of a PLL at the block diagram level:

[(Ref LFO) times (trem LFO)] -> [low pass filter] -> [trem LFO]

But, how to implement the circuit eludes me for the moment. I am reading through the instructional texts and datasheets for discrete Gilbert cells, PLL ICs (e.g., 4066, 4046), and balanced modulator/demodulator ICs (e.g. 1496). Most of the discussion I find concern MHz and greater frequencies and though I did find a reference to a sub-hertz oscillator there was no circuit description. I have breadboarded a Gilbert cell with bipolars but have not gotten it to work yet. It is not clear from where the output should be taken or just how the inputs are setup.

So, is this a good or bad idea? Which, if any of the ICs or the Gilbert cell is "better?" Would something other than a JFET be better for the variable resistor in this case? Any other thoughts?

[R.G.]

Good project, and good thinking!

PLLs are remarkably useful for syncing of all kinds. They get very tricky when you start looking at different types of phase detectors and filters. The overall PLL has a time response in terms of seeking and maintaining lock and following transients which produces the same artifacts as do a voltage amplifier with feedback filtering - step response, overshoot, damping, ringing, and even oscillation and noise.

For very low speed systems like this, the first thing I would worry about is limits on everything. For instance, can you set up and run that LFO you're trying to control by manually feeding in a voltage from a pot wiper? If so, what is the range of voltage it will accept on the JFET gate and still keep working? That's the working range of control voltages your PLL has to turn out to control it.

Next, I'd worry about the slewing speed of the oscillator. If it's running in the middle of the input voltage range for the JFET input, and you feed it a step in control voltage of, say, 1/4 of the good range, how fast does it stabilize all by itself?

With that in hand, can your phase detector turn out a matching voltage to drive the JFET input?  I would test that by hooking up the PLL to the LFO, but breaking the loop for the PD to the JFET on the LFO. Then I'd set a middle-of-range reference frequency into the LFO and break the loop between the loop filter and the JFET/LFO input. Driving the JFET gate with a pot voltage in the range you discovered in the first test, does the PD/filter turn out a useful voltage range and direction?

If the PD and filter can't turn out a good driving voltage for the JFET to operate, it can't work. And if the JFET can't drive the captive LFO to the frequencies it's being told to get, it can't work.

The challenges are that at very low frequencies it's hard to see the thing locking up or unlocking. On top of that, acquiring lock in the first place may take quite a while, as the PD/filter of the PLL may take many cycles to lock; once locked, there is a maximum slew rate the reference frequency can do and keep lock.

[amptramp]

Another device you might want to look at is the LM565 which is a PLL with an internal Gilbert cell phase detector.  If you narrow your detection bandwidth, you may get better noise rejection but may lose the ability to lock in quickly on wideband signal inputs.  There was a clever circuit in one of the early Hoffman colour televisions (from about 1954) called a quadricorrelator - it determined whether the PLL for colour subcarrier regeneration was synchronized and awitched a capacitor in parallel with one that was already there.  With the PLL unlocked, the cap was not in and the filter was set for a higher rolloff for fast acquisition.  Once lock was acquired, the extra cap was switched in to reduce the bandwidth and reject noise.

[R.G.]

Thanks, amp. That brought back something that was pertinent, but got lost before I quit typing.

If the gilbert cell is for the phase detector, I recommend doing a different phase detector. An analog multiplier does work as a phase detector, but it introduces issues with locking. It's fast, but has a limited lock range. The switching setup to get fast locking but still good, low ripple error voltage is one way around it.

I much prefer digital phase/frequency detectors. The detector in the CD4046 and its descendents is an amazingly good fit to most PLL applications. The only issues with it are that it has to have a clean edge to work from. So a comparator on the input frequency is usually needed. This can sometimes be done with a Schmitt trigger input gate. The PD in the 4046 will lock for any frequency in its VCO's range, and will not lock on harmonics, which is a problem with simple multiplers or XOR phase detectors.

[boogietone]

Thanks guys.

This is my first time working with phase detectors, etc. So, I am just getting my feet wet.

R.G., your comments concerning response time and settling rate had crossed my mind considering that some of the documentation mentioned minimum frequencies in the kHz range. I know that I will have to deal with this issue. From what I understand, a good "initial guess" and careful management of step changes in frequency make a difference. Once I am up and running, this feeling will (probably quickly) change, but for the studio setup, I am less concerned with sync time than with being able to get synchronized. For the moment, 10s of seconds would be acceptable. This is problem 3 and I will keep it in mind as I move forward. Looks solvable.

I have rigged a JFET as a voltage controlled resistor in the LFO up on the breadboard with source and drain resistors (forget the values - they was essentially picked at random) and it does work with a 100k B Pot set as a voltage divider between 9vDC and ground feeding the JFET's gate from the wiper. Maybe I just got luckly here. Thus, the LFO's frequency seems to be manageable with a JFET given an appropriate bias and control voltage. Biasing the JFET and limiting the control voltage is problem 2. Looks solvable. Other options are welcome.

Problem 1 is implementing the phase detector. I do understand the theory behind them. It is the practical realization this I am working on.

Though I am still going to work through understanding the Gilbert cell, R.G.'s last post has my interest. If I understand correctly, one appropriate way to do this is to square both the reference and the controlled LFO signal up and then work it like synchronizing clock signals in the digital domain. I assume that this is done on just the rising or falling edge. This seems very reasonable and solves one problem that I saw coming. This being that for the Gilbert cell/multiplier type phase detectors, the relative amplitude of the signals affects the result, meaning that either the different amplitudes of each signals would need to be the same from use to use and an appropriate factor built in to the detection circuit or an onerous calibration would be needed each time I set it up. Neither of which is appealing.

Good stuff.

[R.G.]

This is my first time working with phase detectors, etc. So, I am just getting my feet wet.

C'mon in. The water's fine. 

I am less concerned with sync time than with being able to get synchronized. For the moment, 10s of seconds would be acceptable. This is problem 3 and I will keep it in mind as I move forward. Looks solvable.

If you can wait that long for a synch, you're in good shape.

Imagine for a moment that you have a magic phase detector that will do exactly whatever you describe it as doing. The perfect phase detector would produce an output that was zero (or some middle bias value, same thing) if the two waveforms were exactly in phase, and would linearly ramp from 0 to +Vmax if the phase led, and from 0 to -Vmax if the phase lagged. That's what we want.

However, the phase detector doesn't get that much information. Each cycle, it can only say what the phases were on that one cycle. Analog phase detectors, like a Gilbert multiplier cell, do this faster than digital ones, which compute phase delay from edges (zero crossings). The analog phase detector is fast, but it also tells you about other wiggles inside the cycle, and can easily lock on harmonics that fake out the multiplier with information not about the lowest frequency.

Digital phase detectors work only on edges (if done well  ) and compute the phase difference on a cycle by cycle basis, as a pulse width, not an analog product of the multiplier. So they have to be averaged more. They pay back this slowness by not locking on harmonics (again, if done well).

Both kinds of phase detectors need averaging after them to average down the phase error voltage so the controlled oscillator doesn't jump around all over the place. Averaging by its nature takes several cycles. If the phase detector is perfectly linear, and the controlled oscillator can respond instantly, then the error voltage still slows things down.

It's normal to expect a PLL to take many cycles to lock if the incoming signal is not near it's present frequency.

I have rigged a JFET as a voltage controlled resistor in the LFO up on the breadboard with source and drain resistors (forget the values - they was essentially picked at random) and it does work with a 100k B Pot set as a voltage divider between 9vDC and ground feeding the JFET's gate from the wiper. Maybe I just got luckly here. Thus, the LFO's frequency seems to be manageable with a JFET given an appropriate bias and control voltage. Biasing the JFET and limiting the control voltage is problem 2. Looks solvable. 

Cool. If what you have works, use it!

Problem 1 is implementing the phase detector. I do understand the theory behind them.

The phase detectors on the CD4046 and its descendents the 74HC4046 and 74HC7046 are so good, I will go to some trouble to use them instead of cooking my own.

If I understand correctly, one appropriate way to do this is to square both the reference and the controlled LFO signal up and then work it like synchronizing clock signals in the digital domain. I assume that this is done on just the rising or falling edge.

Yes. You do your best to clean up the input to a single rectangular wave with definite edges. This is one of the prerequisites for the 4046 et. al.

This seems very reasonable and solves one problem that I saw coming. This being that for the Gilbert cell/multiplier type phase detectors, the relative amplitude of the signals affects the result, meaning that either the different amplitudes of each signals would need to be the same from use to use and an appropriate factor built in to the detection circuit or an onerous calibration would be needed each time I set it up. Neither of which is appealing.

Yep. There is all that ugly analog stuff to mess with too.

One neat trick is to use the 4046 et. al. as a frequency multiplier and take out, say 64X the incoming frequency. That lets you take the output and do waveform synthesis on it to get out whatever waveform you like as an output, not just a square wave at 1X.

At the risk of confusing things, an LFO running no faster than, say, 10Hz, practically begs for you to take a uC, and time the edges, then create an output wave that is what you want. This is what digital phase locks do in general, but the low speed of the LFO lets you use unspecialized controllers to do it.

[PRR]

Why not just drive the tremolo with the (buffered level-shifted) LFO?