Understanding Electronics

[Dylfish]

Hey Guys,

I've been racking my brain as I want to start understanding whats going on and not just solder some parts to a PCB and hey presto. for my question I will use the schematic for the Noisy Cricket and go from there.

http://www.beavisaudio.com/projects/NoisyCricket/Noisy_Cricket_Schematic.gif

1) Once your signal enters through J1 it is met with a resistor in parallel at R1. I know this is to stop switch popping, but my question is where does the signal go? Does it go down R1 and to ground and back up and continue on the series connection between J1 and Q1, Or does it go down straight to ground whilst the rest of the signal goes straight from J1 to Q1. I guess I mean if the signal comes through a circuit and had many places it can go, what means it will go some places and wont be affected by others in the setup.

Sorry if the question is a bit confusing

[greaser_au]

For this sentence ignore the input jack. R1 references the JFET gate to ground (such that it's gate is pretty much at zero volts) so the JFET's gate will be (negatively) biased by the (positive) voltage on it's source. This is done so that the JFET is operating somewhere in it's linear operating  region. The voltage on the source is developed across R2 by the current flowing through the source/drain, and thus through R2.

The JFET is a voltage sensing device - and in a perfect world it's input resistance would be infinite.  so for analysis of the input we can ignore the presence of the JFET.

The signal voltage across J1 is also across R1- the current though R1 is pretty much negligible from an operating perspective, but non-zero.  It DOES form a voltage divider with the output resistance of the device plugged into J1, (actually impedance (Z), but we'll ignore that also for now - did you ever study 'complex numbers'?)   reducing your unloaded signal voltage voltage by the ratio  R1/(R1+Rs) - if the output resistance of the device plugged into J1 is 100k, then the your signal at J1  will be 10/11ths of unloaded (not much difference.. ) Further, R1  presents a consistent load to anything connected to J1.

To operate as an amplifier the JFET sniffs the voltage across R1 with it's gate, and uses it to control it's output.

I hope this helps
david

[merlinb]

The input signal voltage hits the gate of the JFET and goes no futher. The JFET looks at the voltage on its gate and sort of copies it, generating a current. This current flows in R2, so a *new* signal voltage develops across R2. This voltage is coupled through C2 to the next stage of the circuit... Then something similar happens again and again inside the IC.

The point is, the "signal" is not really a single 'thing' that finds its way through a circuit from input to output. It's not a laboratory rat in a maze. The current coming out of the guitar never gets anywhere near your speaker!
It is really a whole sequence of copies: you send the signal to one transistor, it copies it (as best it can, or maybe very badly!) and then passes it on to the next transistor...and so on.

[Dylfish]

so your saying that you could / should break a circuit up into areas or nodes and go through it one by one to see what is happening?

Thanks guys

[greaser_au]

yes, it makes things a lot easier,   it's called the 'systems approach'.   Basically you break the circuit into 'black box' blocks (also sometimes discussed as 'four-terminal networks'). What is inside the blocks is irrelevant, only what it does and how it looks to the 'outside' (the other blocks connected to it). Each network has a number of parameters, input impedance, transfer function (in both directions, though usually the output->input effects can be ignored), and an output impedance (the battery supply is irrelevant in the consideration and isn't one of the 4 terminals - if you wanted to go REALLY crazy you could even factor it's characteristics into the stage analysis!).

When you need to analyse a stage you ignore the external & 'step inside' the boundary of of the black box.  You can make this analysis as rigorous as you want (what the EE does) or as cursory as is required to get an idea of what to expect (what the serviceman does).

david

[greaser_au]

Now I am going to embarrass myself and show how rusty my memory is...  

As an example:  we have a 'black box'  between J1 & C2:     the junction of R1 & Q1 is terminal 1, ground is terminal 2, the junction of Q1 & R2  is terminal 3 and ground is terminal 4 (we'll leave C2 outside as it will add complex impedances!) To analyse the stage at a servicing level, you step inside the box & try to work out what sort of stage it is - I can see that the input is on the gate & the output is on the source- the drain is connected to an AC ground via C1 - it is therefore a "common drain" stage.    See http://en.wikipedia.org/wiki/Common_drain for the maths to calculate it's parameters. We know that this sort of stage will have a high input impedance, a low output impedance, will be non-inverting and will have a voltage gain of slightly less than 1.  

We need the FET's gm, but it's a wild guess based on assumptions & estimates... basically (using randomly selected median values from the datasheets min/max values)  if we assume the source is at 3.3V (thus the source current (Is) is 1mA), the Vgsoff is 6.6V, and the Idss is 10mA the gm pops out at 1.5 mS (milliSiemens).    (gm = |2 * (Idss/Vgsoff) * [1 - (Vgs/Vgsoff)]|)   So we have:

Input impedance:   R1 in parallel with the internal impedance of the FET  gate (infinite),   =  1Mohm,    
Transfer function:   the maths says it has a voltage gain of about 0.85.
Output impedance: the maths says it will be about 550 ohms.

So between terminals 1 & 2 it is basically a 1M  resistor (which is what the device plugged into J1 sees),    and between 3 & 4 it is a voltage source (of (0.85 times  the voltage between terminals 1 & 2) +a 1V offset created by Is) in series with a 550 ohm resistor  (the output impedance may need to be taken into account when loading the circuit with a following stage).

The EE would include at least the gate capacitance, the source capacitance, the impedance of the power supply,  and would make a much more rigorous determination of gm.

david

[Dylfish]

thanks heaps david, now to sort through it all