JFET Resistance and Input Voltage Limitations in Phase 90

[YouAre]

I'm trying to understand two things about the JFET's in the Phase 90 Circuit. ( http://www.electrosmash.com/images/tech/phase-90/mxr-phase-90-script-logo-schematic-parts.png )

First, using this link to calculate RDS ( http://www.learningaboutelectronics.com/Articles/How-to-calculate-the-drain-source-resistance-RDS-of-a-JFET-transistor ) and a range of values from this datasheet for VGSoff and Idss ( https://www.fairchildsemi.com/ds/2N/2N5952.pdf ) of -1.3 to -3.5V and 4-8ma respectively, I'm getting RDS to be around 60-120 ohms. That seems awfully low. For the Value of VGS, I'm taking the difference between the LFO output (4-6V) and Vref (4.9V).

Simulating the pedal in spice, with these values in parallel with the 22k Resistor, I get the lowest notches at 500HZ and at 3K. This is much higher than what I've seen one frequency response graphs of the phase 90. ( http://www.electrosmash.com/images/tech/phase-90/mxr-phase-90-frequency-response.png ).

Can anyone offer some insight as to how to properly calculate the Rds resistance in this case?




Speaking of LFO's, I'm also looking to modify the Phase 90 LFO. I've posted a previous thread about replacing the LFO with the ramp style VCO as shown in the geofex schematic (http://www.geofex.com/FX_images/p90ramp.pdf) and have successfully implemented it. To spice things up a bit, I want to modify the output of the LFO to resemble the runoffgroove Tri-Vibe (http://www.runoffgroove.com/tri-vibe.html) to create a more "lumpy" LFO swing. In LTSPICE, I can simulate a retrofit for the LFO to have the same waveform, but of course the output is much larger. I would like to tailor it as such to be in a safe range for the JFET. What input voltages can the JFET handle in this case? I can also understand if there is a range of voltage within the confines of the phase 90 pedal that have no effect on the operation of the pedal, because we'd be pushing the JFET out of the region in which it acts like a resistor.

Thank you for the help and insight!

[jatalahd]

Typos in equations are not so obvious than in plain text, good test is to check if the units are matching ... The RDS equation provided in that link does not give the units of resistance. The equation is missing a voltage term in the numerator, since we need to have V/I for resistance. The correct term in the numerator is (V_GS,off)². Otherwise the formula is "legit".

Anyway, I would not focus too much on the calculated values when it comes to the drain-to-source resistance of a JFET, the variance is just too high. Also the given equations are based on theoretical idealisations of either exponential or uniform doping distribution of the JFET substrate. Hopefully the following picture gives a rough idea on the topic:
 
The theoretical difference between the exponential and the uniform doping is not that significant, but the nonlinearity of the Rds makes it useless to try to evaluate anything decent between the limiting points of pinch-offed and fully conducting JFET. All you need to know is that at pinch-off (V_P or V_GS,off) the resistance is infinite, and already a few hundred millivolts above the pinch-off, the resistance is typically down to a kilohm range.

This is why the JFET is connected parallel to the 22k resistor. When JFET is at pinch-off, the parallel resistance equals 22k, this is your other limiting value on the all-pass filter. When the JFET is is conducting, the resistance is around a kilohm or less and the parallel resistance is ruled by the Rds of the JFET. Please note however that each JFET is an individual an the Rds might differ significantly even between the same JFET model.

My experience is that it is good to have the LFO sweeping close to the pinch-off, just hitting the pinch-off voltage at the low end and going about 0.5 - 1.0 volts above the pinch-off at the high end. This way the sweep should be relatively symmetrical.

Hopefully this answers at least some of your many questions.