When buffering V+ with an Opamp do I need series resistance on the output?

[Bill Mountain]

For example.  I'm working on some CMOS circuits and I was consider using a pot as a voltage divider on the power supply and then buffering it to keep the varying resistance from effecting the current on the CMOS V+ pin.

My question is whether or not the opamp will be stable without a series resistor on the output of the buffer before the V+ pin of the inverter chip.

[nick d]

  The V+ input is VERY hi- impedance , so resistor would make no difference . A capacitor from V+ to ground is a good idea , doesn't hurt to put one on the output either .

[nick d]

     Ahhhhhh.... was thinking of the non-inverting Op-amp input .
     
       From the Op-amp output to the CMOS supply , a small series resistor and a cap to ground is a good idea .
       If you make the resistor large , you might get " starve "  effects , which can be fun , if that's what you want !

[bool]

A bjt buffer (configured as a capacitance multiplier) with some added resistance in collector(!) to decouple from rails may be a better idea than using an opamp. My 2c.

[Bill Mountain]

Well...basically I just want to adjust the voltage to the inverter and hear the effects it has without the current being adjusted at the same time.

[amptramp]

As you move the bias on a CMOS device away from either rail voltage, the current through the CMOS inverter will increase to about 8 milliamps at Vcc/2 and the resistance applied to the gate inputs does not really matter.  The gate diodes only conduct if the input goes a diode drop beyond the rail voltage in either direction.  If you get 9 volts and 8 mA, you have 72 milliwatts in each inverter section that is operating in the linear mode, so don't assume CMOS will give you a low current drain.