Maximum gate-drain voltage in a MOSFET?

Started by merlinb, September 08, 2014, 03:46:30 PM

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merlinb

Can someone tell me how much voltage a MOSFET can take between gate and drain before frying? This doesn't seem to be something given on data sheets. I'm talking of course about the 'incorrect' polarity, when the drain might accidentally be pulled below the gate. Are we talking volts, or do I need a gate-drain protection diode?

R.G.

The gate is isolated from the channel by a layer of high-purity glass 20-30 volts thick. You'd probably need a gate protection diode, except for the body/substrate diode. Pulling the drain the wrong way turns on the body diode when the voltage gets over a silicon junction drop.

This was the trick in the MOSFET polarity protector - the body diode conducted, and the gate would enhance the channel enough to get a channel resistance with a voltage drop below the body diode voltage. When the voltage was wrong, the gate was not enhancing the channel and the body diode was back biased, so nothing flowed.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

merlinb

#2
Quote from: R.G. on September 08, 2014, 04:06:04 PM
The gate is isolated from the channel by a layer of high-purity glass 20-30 volts thick. You'd probably need a gate protection diode,
Hmm, but for an IRF820 under normal conditions the drain might be 400V more positive than the gate, yet this does not break down the gate-drain insulation. How come?

bool

But you asked what happens when drain is below gate - or in other words, gate is (way too high?) above the drain - if I understood correctly?


merlinb

Quote from: bool on September 08, 2014, 04:43:58 PM
But you asked what happens when drain is below gate - or in other words, gate is (way too high?) above the drain - if I understood correctly?

Yes, RG has put my mind at ease there. As long as the gate-source is protected by a zener, then the gate-drain will automatically be protected too.
But I then because curious as to why the 20V-thick glass doesn't break down with 400V between drain and gate!

R.G.

#5
I always wondered about that, too. I believe it's to do with the physical layout of the channel vs the gate overlay. Someday I'll need to know that enough to go look it up.

Edit: I got curious enough to expend a search on it.

See: http://electronics.stackexchange.com/questions/16289/why-is-a-mosfet-triggered-by-vgs-and-not-vgd for a rambling, inconclusive discussion of the issues.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

PRR

Rather a good question.

Since the Gate oxide is only ~~20V, yet they sell them for use with Drain at 500V and 1,000V, I had ass*umed it was OK to run 1,000V from Drain to Gate. Obviously it is.

But how can that be?

We know that when any FET has voltages applied we can get a "Depletion Region" where the crystal is starved for conductivity. In nearly any practical use there will be an area near the Drain which is "pinched off", "does not conduct". This is true even when the total device is conducting (electrons will "tunnel" in Quantum ways). In another view, there is a semiconductor junction diode formed by electric field near the Drain. (This virtual diode is why MOSFETs have 50V or 500V breakdowns.)

Here's a simplified MOSFET showing the internal field. (Yes this is a Depletion device but it is all relative-- just a matter of whether they dope it normally-on or normally-off.)


(Similar but in Italian: http://eletronicos.etc.br/wp-content/uploads/2010/03/transmissor41.jpg)

Perhaps a better picture:
http://www.nature.com/nature/journal/v479/n7373/fig_tab/nature10676_F1.html

The Gate-Drain voltage pushes charge carriers away from the Gate. But the Gate-Drain voltage is much larger and pushes even more, totally "pinching" the channel.

I am speculating that this pinched-off region acts as additional insulation.

OTOH, two insulators in series will split the voltage in proportion to their resistances. The Gate "glass" is perhaps the highest resistance stuff on the die, so the glass should take most of the voltage. However the charge carriers swept out of the depletion region are very mobile, so maybe if the least voltage appears through the glass, they move away more, tending to reduce the electric stress on the glass.

BTW, off-topic: Lilienfeld's 1925 patent was drawn so broadly that AT&T could not patent their silly 1947 crystal until they negotiated with Julius. US # 1,745,175
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