Layout Tips for BBD circuits.

[mth5044]

Anyone have any tips for laying out PCB's for circuits with BBD's and clocks and whatnot? Not a lot of gain stages going on, so I don't think linearity is quite as important as in a Dr. Boogey, but what about clock placement? Should audio processing be kept on one side of the PCB and the clocks/modulation kept on another, joining at the BBD? Should the clocks be on a separate ground pour or even a seperate board with star grounding? Any tips about this or anything else really is much appreciated.

Danke

[armdnrdy]

I posted this not too long ago.

http://www.diystompboxes.com/smfforum/index.php?topic=109774.0

When I was working through this project, I took notice of the great board layout. It's kind of textbook with the BBD/Clock section separated from the audio path. You'll notice the grounds from the two sections separated as well.

[mth5044]

Nice example, thanks! Seems like a pretty standard way of doing it is audio, BBD, clock from south to north. That was a weird way to say that.

Anyway, I was looking at the grounds and it looks like they are one solid fill, but it snakes around a lot? You had mentioned they were sperate - perhaps you meant by space, not actually two different pours? I wonder if it's different for different clock rates - for example less necessary in delays, but becomes a problem with flangers or something

[armdnrdy]

It's all about the layout.

If you look at most of the older flangers..they were single sided boards.

The "separate" ground I was referring to is the split at the center of the board. North of the split is BBD/Clock ground, South is signal.
And yes...they do join together eventually.

[Fender3D]

It is written: "BBD does not live by GND alone, but by +Vcc and clock also"... 
separate or decouple them as well...

I noticed that it's really more important having clock tracks as short as possible, and not too close to GND pour or tracks.

[armdnrdy]

Here! Here! 
All about the layout!
I've found out the hard way a few times...now my routing is a bit more proactive.

[Cozybuilder]

Not PCB, but this is my layout for a Zombie Chorus on perf using MN3007 BBD for a 1590LB build:

[R.G.]

The higher the frequency, the easier it is for signals to "leak" out into the universe by capacitance, inductance, or RF emission. Nearly-vertical "edged" on signals and sharp corners or points on signals are composed of high frequency harmonics. Clock signals almost by definition have sharp corners and near-vertical edges. So clock signal voltages transmit easily through parasitic capacitances, and clock signal currents are easily transformed and impeded by PCB trace inductances.

That means that on a PCB, for clock signals - well, any logic signal, really - you want
(1) SHORT traces. You can't get clock/logic signal traces too short. Shorter traces have less parasitic capacitance and inductance, and the antenna-characteristics of the trace are terrible, so it can't radiate out very well.
(2) DIRECT traces. Straight lines. Don't go weaving these things all over the map. It just adds length in violation of (1), adds capacitances to every trace it passes and add mutual inductance to all the traces it passes to couple in those sharp edges.
(3) DISTANCE from traces carrying high impedance signals, like analog inputs, the (+) input to opamps, and the inputs to MOS, MOSFETs, and CMOS gates.
(4) STUFF BETWEEN TRACES in the form of ground or low-impedance-to-ground  traces to soak up some of the detritus that spills off the clock traces

And for ground, nothing beats knowing what currents flow in what traces. You want the fast-edged stuff to flow in its own ground conductors when it's returning to the chip that sent it. The origin of analog versus digital ground was to force the separation of digital ground currents into a sloppy, but tolerant set of ground conductors on the digital side, where the chips don't care much if a signal is 0.0000000V or 0.9V - both are logic "low". In the analog ground, you'll hear it if ground isn't 0.000000V. Connecting logic ground and analog ground in one and only one place means that there can never be common currents through them. Current flows in LOOPS.

[tubegeek]

Is there anything to be gained by filtering the clock signal into a less-square, more-sinusoidal shape to reduce its tendency to spew noise? (Reduce the highest-harmonics content.)

Don't logic signals trigger OK so long as they rise to an adequate voltage - is the sharpness of that rise so important?

It's not like we care too much in analog audio about microscopic time inaccuracies along the slope of the rise - we're not worried about jitter, we're just turning stuff off or on, usually, right?

It seems to me that approach might reduce the very common problem of tremolo "ticking" but I don't know from experience, I'm just throwing it out there as a question.

[Digital Larry]

Sometimes a series resistance is placed in a data line, or more likely all 8, of a CPU bus to help reduce radiated interference.  That will help cut down the current spikes that happen on those edge transients.  But I don't have a good rule of thumb as far as the value goes.  Usually I've seen values between 33 and 100 ohms. 

[R.G.]

Don't logic signals trigger OK so long as they rise to an adequate voltage - is the sharpness of that rise so important?

As Yogi Berra said "In theory, theory and practice are the same. In practice, they aren't." Logic comes in various varieties. Some logic is level sensitive, what you describe, and some is edge-triggered. The edge triggered stuff needs an EDGE and the specifications have critical maximum rise and fall times. Then there's the issue of when the clock edge (or clock level) hits on the rise/fall slope of the signals it's clocking.

So yes, it can matter.

That being said, too-fast clock edges can be a problem, as DL mentions, you get current spikes and radiated pulses. And other stuff. If you want to get deeper into this than you probably do, go get a copy of High Speed Digital Design: A Handbook of Black Magic (http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241). It gets deep. This is one of the more readable texts on it.

For our baby-steps logic stuff, good grounding is usually enough. Slowing down the rise and fall times for CMOS is good, and can often be done by either series limiting (per DL), or source or load terminating nets, or some combination of all the above.

And to answer the original question, yes, slowing down the edges one way or another is good, as long as you don't get tripped up by minimum edge speeds on edge-triggered logic.

[highwater]

I find that suggestion quite intriguing. I'm curious if my initial guess regarding how BBDs would respond is anywhere near correct...

Using the MN3007 as an example, because I easily found a datasheet that shows a simplified internal circuit, here is what I can figure:
1) Max rise- and fall-times for the clocks are specified as 500ns.
2) During the rise- and fall-portions of the clock cycle, the MOSFETs are neither fully conducting nor fully shut-off... and the in-between characteristics are not specified.
3) The BBD is *not* edge-triggered, but rather level-triggered.
4) If the two opposing clocks are ever *both* high at the same time, all of the storage capacitors will be trying to equalize charge with each-other.
5) If the two opposing clocks are ever both low at the same time, nothing bad will happen, but... you suffer from the leakage-related effects of a lower clock-speed *and* the charge-transfer limitations of a higher clock-speed.

So, in short, it should still work OK with slower clock transitions, but fidelity will be (perhaps greatly) reduced? Or am I completely wrong in my assessment?