Question about attenuating signal before a JFET buffer

[gregwbush]

Hi

Just a quick question...

In the following 2 circuit snippets, would the output level be the same? I.e. aprox a 1000:47 reduction (set by the 1M/47k voltage divider easily visible in the right circuit)?  I'm looking to use the left circuit's method of biasing the jfet and I must have a 1000/47 gain reduction. I'm just not sure what happens having 2 47k resistors there.



Or in other words, what i really want to know; What's the simplest (lowest parts count) way to rig up a single supply JFET buffer with 1000:47 gain reduction before it and having an input impedance of aprox 1M?

Thanks

[anotherjim]

Because the power supply has low AC impedance, the 47k split resistors actually act in parallel - so you need 2x 100k instead, which of course is actually 50k.

[duck_arse]

1000:47? what kind of ratio is that? I was taught in maths class that a ratio is always expressed "to 1". then, no matter how convoluted the actual, real-world generated numbers are (1000, 47, 1), you can compare directly one ratio and another.

is 1000:47 anything like 21.3:1?

[TejfolvonDanone]

Actually with 1M and 47k it will be 1047:47.

I was taught in maths class that a ratio is always expressed "to 1"

It just makes the ratio more "readable". pi:e is a valid ratio but doesn't tell you much.

The first uses more resistors so the second has the smaller part count. Also i think you should bias the JFET to ground not V+/2.

[R.G.]

Actually, with a 1M and a 47K, you don't need the JFET buffer in most cases. Unless the JFET is driving a quite low impedance for some reason, the output impedance of the two resistors by themselves is a bit under 47K.

That is, if you really want to save parts  - which itself needs more explanation; why?? - you'll need to tell us more about what you're doing.

[PRR]

> I was taught in maths class that a ratio is always expressed "to 1".

This isn't maths class.

Engineers should start with the actual values to reduce confusion (which this project already has). 1000K:47K. Any grizzled engineer can reduce that to 20:1 (and do the +1 if warranted) mentally. "21.3" is unwarranted precision with +/-10% resistors and a JFET that will fall ~~10% shy of unity gain.

Not sure why you want an input which will accept over 21.3V inputs. Most such HIGH-level sources don't need 1meg loading. You may be over-killing a problem with a simpler answer.

+1 to R.G.'s point. (Will you guys quit posting faster than I can type?<G>)
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> The first uses more resistors so the second has the smaller part count.

Only if a Vref is already on-board.

In general the left plan inserts half the supply crap to the (reduced!) signal. We can't assume all supplies are squeaky clean. A Vref can be filtered.

> bias the JFET to ground not V+/2.

Then the peak output is not even the JFET's threshold voltage. V/2 biasing gets closer to half the supply voltage before clipping. At least for low Vto JFETs, half supply bias is probably better. If you are using-up a pile of high Vto devices, Gate at zero may be acceptable and simpler.

[R.G.]

It occurs to me that I left off some important advice, not about this particular problem but all electronics in general.

This circuit, like so many others, practically all others on the net, is incomplete. It completely ignores two things that are a crucial part of the circuit: whatever drives the input, and whatever loads the output. Without knowing these things, you can do no more than guess at what might happen.

The signal source driving a circuit and the load on the output are critical parts of circuit design.

[gregwbush]

Good information in there, thanks.


Here it is in context.  4ch tube amp i'm building's FX loop send idea (perhaps a stupid idea as i progress)





I've already done this in another amp with a dual supply OP amp buffer and 1M/47k divider (~20:1 LOL) in front and it's functioning great. Same driving circuitry more or less (cathode follower into tone stack into 4 volume pots into relays). After that is a recovery op amp (~20:1 gain) driving a master volume and the phase inverter, in parallel with a unity gain op amp buffer driving a post FX line-out. That's 3 op-amps

I was thinking jfet here for one main reason... space on a circuit board. I could drop one of the aforementioned op-amps and use a jfet instead.  It's not a valid reason now that i've looked at it a bit.  Might as well squash another op-amp in for better (noise) performance etc, which is how i drew it up originally anyway....

[PRR]

> in context

OK, so you have 80V peak from around 1Meg, and you want to expose this to external FX boxes.

One observation: four 1Meg pots parallel is a 250K load on the tone-stack. This significantly limits the amount of bass-lift possible, and makes the top of the Bass pot somewhat pointless.

OTOH 1Meg pot is already rather high for full frequency range audio. Wiper half-up, it looks like >250K, and 60pFd of stray capacitance will be down 3dB @ 10KHz, 1dB at the top of guitar.

It begs for a buffer between tone-stack and pot-array. But this will be a beastly buffer to handle 80V peaks and <200K total load. 12AU7 biased grid near half-supply and <100K cathode resistor, 2mA-3mA current.

Thinking allowed..... what about your buffer right off the tonestack, then four 100K send pots and the relay matrix? Or do you have FX which will load a 100K pot?

[PRR]

> with a dual supply

If you have dual supply-- wire the JFET D to +15V, G to zero V, S through 10K to -15V. Bias is clean, well-defined, and headroom is doubled. (Not that an external FX loop should need +/-10V swings....)

[gregwbush]

That's awesome PRR. Good info as always.

I might end up with something like this then




Do i need dc blocking caps with a bipolar supply then? I feel like there should be one at the output of the buffer. How about the input? I also feel there needs to be a pulldown resistor after the relay matrix to avoid a pop if some DC get's there somehow. Does 1M make sense there or would i make it 100k or 10M?

[TejfolvonDanone]

Do i need dc blocking caps with a bipolar supply then?

Again it depends on the source and load. This time the tone stack's 3 caps block all the DC coming from the tubes. For the output  you need because you drive the FX send and it isn't a nice thing to send DC to (although nothing really bad should happen). The pull down resistor isn't needed in my opinion because the 4 pots are acting as a pull down resistor for the output cap.

[gregwbush]

For the output  you need because you drive the FX send and it isn't a nice thing to send DC to

and scratchy volume pots potentially yes?

The pull down resistor isn't needed in my opinion

What say it feeds a pedal or other device that has a capacitor on it's input with no pulldown resistor? DC will build up there and go POP when the relay flips. Perhaps i'm being over cautious do you think?

This time the tone stack's 3 caps block all the DC coming from the tubes

What about the other way though, can DC come from the transistor's gate and onto the tone stack pots where it would make scratchy noise? Or is that irrelevant?

Always more questions than answers with me.


What about the following...
The recovery stage. Does that need re-jigging?

[TejfolvonDanone]

and scratchy volume pots potentially yes?

Scratchy pot will be a scratchy pot even with the cap.

What say it feeds a pedal or other device that has a capacitor on it's input with no pulldown resistor?

Then that pedal isn't well made. You aren't responsible for that. And if that pedal has no pull-down resistor then it will pop even with your pull-down resistor.

What about the other way though, can DC come from the transistor's gate and onto the tone stack pots where it would make scratchy noise? Or is that irrelevant?

In normal operation there can't be DC voltage if you bias with ground. If you put V+/2 on the JFET's gate resistor then you just mess with the bias of the JFET. In this case you also have to connect the mid pot to V+/2 to avoid bias variation.

On the recovery stage you should put an input cap in case the FX return sends DC. For a rule of thumb every input and output should be AC coupled (in other words there should be a DC blocking cap).

The FX should have the buffer if a) the phase inverter gets a bigger level without the FX loop b) the phase inverter's input impedance isn't high enough.

[gregwbush]

Thanks again for your input.

Here's where it's at now.  The divider has changed to 470k/22k.  This is because i want the tone stack to respond more like it's connected to 2 parallel 1M pots feeding a phase inverter (of about 2M input impedance) like it does in the amp i copied the tone stack from. 2M||1M||1M = 400k.



I got rid of the jfet completely.  Bread boarding delivered unsatisfactory results as far as power supply noise rejection is concerned.  Buzz.  The op amp is just about silent.  The supply i'm using is very simple; a non-center tapped half wave bipolar arrangement. 2 diodes and 2 capacitors. No regulation.  Something like this:




So this is officially completely off topic. No jfet!  Thanks for reading