Jfet Matching with the Peak Atlas DCA75

[chromesphere]

Hey guys,

Tinkering around with the DCA75 again, this time with jfets.  I know its probably overkill curvetracing jfets for matching but hey, i've got it here infront of me so what the hell?
Also, before i start, please understand i have only the most basic understanding of how a jfet works so please forgive my termonology etc.

So the question is pretty simple i guess.  Can you use the Id / Vds curve tracing ability of the DCA75 to match jfets?  In the graph in the link below you may be able to see there are 5 jfets that have a very similar vds/id curve.  I assume as these devices react similarly in this test they will work "similarly" in a phaser (yes the phase 90).

https://postimg.org/image/bu2z4ls1t/

One more question, the values picked for VDD (0 to 10v) and Vgs (-1.1v) were handed to me automatcially by the peak atlas software.  Wondering if these are optimal for the conditions we need for testing in phaser circuits.

Thanks for any help or insight.
Paul

[TejfolvonDanone]

Can you use the Id / Vds curve tracing ability of the DCA75 to match jfets? 

If i'm not mistaken you want to get the pinch off voltage and the zero gate voltage drain current.
The first can be easily calculated from the graph but only with large error. The point where the drain current becomes constant is the point where Vds = Vgs-Vp. You only have to find that point.
After that you can calculate the zero gate voltage drain current (Idss) using the jfet's gate voltage drain characteristics and reading the what is the maximum current of each trace. You take the equation: Id = Idss *(1- Vgs/Vp)^2 where Id is the read value, Idss is what you are looking for you know Vgs from the traces and you've got Vp from the previous step.

I don't really know what the DCA75 is capable of but if you can set the gate voltage to 0 you easily get Idss. If watch the Id-Vds traces and decrease the gate voltage you will arrive at a point where the Id will be 0. That's the pinch off voltage (Vp).

[PRR]

> optimal for the conditions we need for testing in phaser circuits.

No. As Szabolcs says, you need to find other points to get a full-range match.

However.... if you look at the corner where Vds is under say 0.2V, the slope is "resistance for Vgs=1.10V", a not unlikely point the LFO wave will pass through. Now you want devices of very similar resistance in this area. Red and Brown are close. Blue is not a good "match" with a Red or Brown device. Green Yellow Violet are a fair triplet. The Orange to Dark Blue quad are a very good match.

[Eb7+9]

look at figure 2 here:

http://www.vishay.com/docs/70598/70598.pdf

we are interested with jFET behavior with zero DC bias ...

that means we're interested with curve profiles in the first and third quadrants ...
ie., around the origin ... (0v, 0mA)

a little digging will produce equations dependent on Idss and Vgs(off) for the rds(on) of interest

Idss, and Vgs(off) are independent values

which is why single variable test methods are really bogus (as mentioned often here ...)

---

it's pretty simple,

>> two jFET devices can be said to be matched if their transfer surfaces match
and vice-versa, two jFET devices with matching transfer surfaces are said to be matched[/b]

data info is typically presented as "discrete" cross-sections as curves ...a bit like a rib-cage
just a practical way of dealing with continuous 3-D media ...

it doesn't matter which Vgs test voltages are chosen in drawing out curve sets
some datasheets will choose 1v increments, others 1.5 or 2 ... it's arbitrary

the top curve is the Idss(Vds) curve ... it should be considered as an important starting point in any testing

now, if the surfaces match then the invidual test curves have to do the same

ie., for devices that are matched Id(Vgs(test), Vds) curves will match at any test voltage Vgs(test)


to be sufficient, one would compare two groups of such curves ...

in your test graph above none of the Vgs=-1.1 curves match at all ...
so, no point going further to see if they'll match elsewhere ... they need to match everywhere

to be clear ...

let's say all of your -1.1v curves did match pretty much perfectly

and then you repeated the test at -2.1v say (assuming that Vgs(off)<-2.1v)

with only some lining-up again there / a possibility that might be overlooked ... (!)

you would then keep those secondary line-up devices as your "final-matched" ones

if you were to test at other Vgs(test) voltages you would find that these ones line-up again regardless of the chosen value ...