mixing tremolo oscillation with guitar signal

[sbirkenstock]

Hi there,

if found this tremolo schematics:
http://www.generalguitargadgets.com/pdf/ggg_eat_sc_improved.pdf

I build an oscillator like that (the part around Q3) (with 2mF caps, since I did not have 1mf) and it works fine.
Now I try to "apply" / mix the tremolo signal to the guitar signal.
I try to understand how it works in this schematic.

Q2 seems to be used as a "variable resistor"?
Than we have the 22mF cap connecting the source of Q1 with the draing of Q2 (therefore I think Q2 is more a switch / variable resistor).
Q2 is supposed to be a Jfet 2N5457. The "oscillating signal" coming from Q3 can only be positive, if I am not mistaken.
Since the gate of Q2 would need a negative signal to change it´s "conducting status", I don´t understand this. Or is Q2 forward biased for some reason?

So my assumption is, that the oscillating part is supposed to change the resitance from drain to source of Q2.
This again is changing the amplifying factor of Q1.
And then there is also C3.
I assume the purpose of C3 is to only have a change in the amplifying factor if there is a guitar signal? To advoid noise at idle?
I might be completely mistaken here...

Can you please give me some hints?

Also, is there another easy method to mix the guitar signal with the oscillation part?

Thank you!
Best regards,

Stephan   

[anotherjim]

Q2 JFET gate-source volts is zero at the oscillator waveform zero crossing - it won't be completely off unless the modulation swings the gate negative enough to reach Q2 pinch off voltage. So Q2 can be constantly changing its channel resistance through all of the oscillator cycle, maybe actually reaching pinch off on the negative peak at maximum depth setting.

As R6 emitter resistor sets the gain of Q1, Q2 having a changing channel resistance will modulate the gain. C3 is critical - this stops the DC conditions in Q1 from following the modulation signal which would carry the modulation to Q1 collector and the output. Only the signal frequencies "see" the effect of Q2 on the emitter resistance thanks to C3 blocking Q1's idle DC current from reaching Q2.

C4 is another important cap as this removes the oscillators DC level and lets the modulation wave centre at 0v so it can reach a negative voltage during the negative half cycle. Remember that Q2, an N-channel JFET, is normally conductive and won't completely shut off until the gate is some voltage more negative than the source terminal.

The more common of the simple ways of doing tremolo is pure attenuation of the signal by using the controlling variable resistance element as one part of a resistive divider. This usually means having a gain stage before or after.

Conceptually, the simplest method is a voltage or current controlled amplifier IC which has one pin for a modulation signal, and you'll find examples of these using the old CA3080 OTA or the current LM13600/13700 type. Somehow, the required supporting components don't make them all that simple.

[PRR]

> The "oscillating signal" coming from Q3 can only be positive

At Q3, true. But C4 and the resistor string tend to re-center it around zero, plus and minus. Then the forward conduction of Q2 Gate tends to cut the + swings so it swings mostly negative. The actual waveform on Q2 Gate isn't clear; but more-than-likely (obviously) it swings Q2 full-ON and very-Off.

The rest of the audio path is an amplifier for Q2 to modulate and to add gain so the trem swings loud and soft relative to the no-trem level.

Probably. That audio amplifier looks over-complicated. But there are too-simple designs that will THUMP your amp loudly. No-amplifier designs are sure to cut signal. Many ways to beat this cat, and I don't know one that is clearly "better".

[Jdansti]

Check out Rich's tremolo here:  http://www.diystompboxes.com/smfforum/index.php?topic=114504.msg1071083#msg1071083

It's got a pretty good mix adjustment (depth) which he demonstrates around 2:30 in the video.

His draft schematic is on page 3 of the thread, but he made some changes which aren't shown. Maybe he'll post his final schem.

[sbirkenstock]

Jim,

I think you answered my "logical" problem.
So if I have some kind of a wave form lets say swinging inbetween +100 and +110 volt, and connect a cap to it that goes to ground through an (rather large) resistor (with C4 this resistance is 438K),
it will not swing from 0 to 10 volt, but from -5 to +5 (relative to ground)?
Thinking about your info it seems logically. The cap is disconnecting it from the "source".
Does this "effect" have a name?

Thinking about it, I can´t believe I missed that one.
It´s like applying a signal through a cap to a biased input (like to a 4,5V Mosfet bias at the gate).

Thank you very much, that was very helpful to me!
Stephan


 

[anotherjim]

I use several terms. Can say ground referencing, de-referencing, re-referencing. Reference can be replaced with "bias", but we also use bias for the no signal "idle" states in an active component. Often the act is implied by the terms "AC coupling" or "DC blocking". Might say "Ground referenced by AC coupling capacitor". Although it isn't the cap providing the reference, it is allowing it. To see what the reference is, you need to read the schematic and see where the resistive (including active devices) paths lead. In the EA trem, after C4, the only ways are to ground.

I missed what Paul spotted about the FET gate diode being forward biased on the positive peak. The modulation can still sound like tremolo if only one half cycle of the LFO wave has effect. You could block the FET diode with a reverse diode in series with the gate, so it only sees the negative LFO cycle, but I don't suppose it would make a worthwhile difference.

[PRR]

> gate diode being forward biased on the positive peak.

"Only at start."

That first positive half-cycle will charge the cap, the average will swing negative. On subsequent peaks there will be a very small burst of current to make-up the leakage in the resistors. The wave at the gate can approach "true sine" and with the tops exactly AT gate diode conduction and minimum JFET resistance (max gain).