Impedance - Frequency response question.

[Chugs]

In Fig1 the 0.47uf cap and 47K resistor form a eq rolloff at 7.2hz. The 47K resistor bias the opamp input at 47K.

If a 47K resistor is added as shown in Fig2 what does this do to the frequency and impedance? Is the eq rolloff still 7.2hz and is the opamp input still biased at 47K?

[teemuk]

Ok, I'll take a stab at this, but in order to provide a clearer example let's ignore source impedance of the buffer and assume input impedance of the opamp is large enough to be neglected. (It's not neccessarily that in real life, depending on opamp used).

In first example you have hi-pass RC filter consisting of 470nF cap and 47K resistor.

In second example you have hi-pass RC filter consisting of 470nF cap and 47K+47K resistor.

So, effectively these two hi-pass filters DO have different turnover frequencies. 47K+47K has lower turnover frequency than the other RC filter, but since signal output is taken from node between those resistors it also introduces a resistive divider that attenuates signal to half of its original amplitude, at least at frequencies above turnover frequency of the RC filter.

The buffer stage, roughly, sees an input impedance of 47K in first example, and 47K+47K input impedance in the second example. That is the total shunt resistance for the source. Yes, practically the RC filter makes it a bit more complicated than that (below turnover frequency) but overall you should get the idea.

As shown in schematics, DC offset -does not change- since the input stage is capacitively coupled and there is no path for DC current through it. In terms of DC the "series" 47K resistor of the circuit #2 is effectively "floating" and will not therefore affect DC offset level. The way the opamp is wired might (the schematic does not show output connections), but for sake of clear example we assume the circuit does not obstruct the 4.5VDC reference bias in later stages.
Series resistance to DC reference is, in both cases, 47K.

[Chugs]

So the input impedance in Fig2 is 94K, (47K + 47K) but the hi pass filter is still 7.2hz? Or is it now 3.6hz? (High pass generated by 94K and 0.47uf)

[anotherjim]

The high pass is between the C and total resistance from source to return. So the 2x47k example is working with 94k.
Think of the connection between C and R as the point of filtering.

Having the resistance split like that to form a voltage divider might be done to prevent the op-amp input exceeding the input voltage range for that chip. The driving transistor stage output can swing 0v to 9v, but the op-amp might not like that.

So the signal the op-amp sees is the filtered version as at the right hand side of the cap reduced by the divider by half or -6dB.

[R.G.]

So the input impedance in Fig2 is 94K, (47K + 47K) but the hi pass filter is still 7.2hz? Or is it now 3.6hz? (High pass generated by 94K and 0.47uf)

The input impedance as seen by the buffer is now 94K. Which does not matter, because we assumed the buffer output impedance was far, far less than that.

More importantly, the input impedance as seen by the input capacitor is now 94K (47K in series plus the original 47K in parallel with the opamp input impedance, which we assumed was much, much higher than the rest of the circuit, and OK to ignore.

So the AC rolloff is 0.47uF and 94K, or 3.6Hz. It was previously 7.2Hz.

Above the high pass rolloff frequency, the signal size as seen by the opamp is half as big as it was with only no series 47K resistor.

That is, it's as Teemuk said.

If you can't ignore the output impedance of the buffer or input impedance of the opamp, and expecially if those are not resistive, but some complex impedance, things get progressively more complicated.

[Chugs]

Ok, makes sense. Thanks for the replies.

A follow up question: In Fig1 the combination of the 0.022uf cap and 100k resistor form a hi pass at 72hz. The 100K resistor also serves as the bias resistor for the opamp.
If we replace the resistor with a pot to control volume, and bias the opamp, does the hi pass response change with different settings of the pot or remain constant at 72hz?

[antonis]

(Although it isn't the most indicated way of Volume control... )

Your pot forms a resistive voltage divider so, any resistance between lugs 3 & 2 is considered in series with Op-Amp Input and any resistance between Lugs 2 & 1 in parallel (shunted).

So we came to your first query case...

P.S.
All depend on the exact point to which we refer to..!! 

Question: You have an Emitter follower followed by another "emitter follower" - I don't know what kind of impendances you want to (mis)match but shouldn't that be more conveniently obtained with a 1M bias resistor & omitting Q3..??

[merlinb]

If we replace the resistor with a pot to control volume, and bias the opamp, does the hi pass response change with different settings of the pot or remain constant at 72hz?

It remains constant, as the input impedance of the opamp is enormous -you can pretend it is an open circuit. The wiper is just sliding up and down and having no effect on the total resistance seen by the cap.

[anotherjim]

Question: You have an Emitter follower followed by another "emitter follower" - I don't know what kind of impendances you want to (mis)match but shouldn't that be more conveniently obtained with a 1M bias resistor & omitting Q3..??

A reason I can think is to have a fixed and constant filter close to the circuit input.
If the emitter follower (or whatever) is the first stage, using its input cap to control bass roll-off is unreliable as we don't know if a low source impedance will be driving it. So make the input bandwidth full range & eq after it.
A discrete input stage can be a very good idea anyway as it don't sound too nasty if driven to clipping & still adds subtle distortion before that.

[antonis]

It remains constant, as the input impedance of the opamp is enormous -you can pretend it is an open circuit. The wiper is just sliding up and down and having no effect on the total resistance seen by the cap.

I hate to do so but I have to disagree with you, Merlin... 

Even if the lower end of the Pot isn't loaded by op-amp input, middle lug is still the point of a voltage divider formed by Xc₂ + R3,2 / R2,1

Or else, we have to consider that the WHOLE signal is lost through C2 & Bias resistor...


edit: My bad, Merlin..
I was thinking of totally different case..

@Chugs: Ignore my previous post...