Input buffer question

[ysba]

Hello!

I'm working in a noise gate circuit. I'm using a 3PDT switch so the effect can be fully bypassed. As it is just a noise gate, the signal must be as transparent as possible when the effect is engaged.

My first choice for input buffer was a JFET with a 10K source resistor because of is high input impedance. For DC blocking filter at the buffer's input I used a 47n and a 2M2 (fc about 1.5 Hz), which give a flat response even in 20Hz, so this circuit can used for bass with no attenuation.

When I made the first measurements with a scope, I noticed that this JFET has a gain slightly less than 1 (like 0,95~0,96). This difference in volume can be heard when I toggle the circuit with the 3PDT switch. The JFET is a J201, and I have tested a J112 with the same results. So I have some questions:

1) Is there some way to make the JFET buffer's gain closer to unit? Maybe replacing the device, input filter components, source resistor...

2) What is the role of the source resistor in the overall JFET buffer performance? We usually see 10K resistors, but it is not uncommon to see 4K7 or 22K. I noticed that changing the resistor's value alters a little the DC biasing pointing at the buffer's output. Can I choose a value that keeps the DC biasing point close to half of supply voltage?

3) As I couldn't figure out a way to solve the question of the JFET, I tried a NPN buffer. I know that it has a pretty lower input impedance than a FET buffer, so I thought in a way to make it higher. For this kind of buffer, we see also the ubiquitous 10K resistor at the emitter. Afaik, the emitter resistor "appears" at the base times the device's gain. So I changed the emitter resistor to 100K, which would act as a 1M resistor at the base for a hfe=100 device. A higher gain transistor would increase this resistance. I've tried this buffer and it sounded pretty awesome in my application, and also I could not see any attenuation at all in the scope in the range from 20Hz to 20kHz.

The question is: is there some problem in increasing the emitter resistor value to 100K? Why do we almost always see a 10K resistor in buffers emitter/source terminals?

I hope you could help me. Thanks everyone!

Yuri

[antonis]

1. Use a FET of higher g_m..
Gain of JFET Source follower is R_S/(R_S + 1/g_m), for load impedance much higher than R_S, so you may alternatively choose a higher value Source resistor as long as Drain current is sufficient to drive output load whereas it simultaneously maintain quiescent Source voltage at desired bias level....

2. See above..
Source resistor value is considered in parallel with driven load so its value is a compromise for setting Source voltage in conjunction with desirable Drain current..

3. Almost correct but with a 100k Emitter resistor you must have a 45μA Collector current to bias Emitter at 4.5V..
This means for 90μA total Collector current (45μΑ quiescent & 45μΑ due to signal variation) your follower is saturated (for a voltage amount of  min V_CE..)
45μA Collector current correspond to 450nA base current for a device of h_FE=100 - even lower for a higher h_FE device..
If you are sure for worst case (temp drift, VBE variation, h_FE spread, etc.) lower than 450nA peak signal current and also for  lower than 45μA output current need, you may safely proceed..

P.S.1
For such a low working current it maybe have to be taken in mind Collector-Base reverse leakage current too..

P.S.2

So I changed the emitter resistor to 100K, which would act as a 1M resistor at the base for a hfe=100 device.

More over as 10M..
(if product of 100k & 100 is 10M..)

P.S.3
For an Emitter(Source) follower (as for any kind of amplifier) design, the main issue is the working current..
(a part of it for DC steady bias and the rest for output load drive..)
A usefull rule of thumb is bias Collector current be about 20% more than maximum current due to signal - otherwise our amplifier is prone to saturation..
i.e. for a signal peak current of 1mA, Collector quiescent current shoud be, at least, 1.2mA..

P.S.4
Do I recently glimpse a ramped-up buzz about "humble" voltage followers or it's just in my mind's eye..?? 

[ysba]

Nice answer! Pretty clarifying. Thanks a lot!

[antonis]

Don't even mention it, ysba..

The above formulae are used for a - fair enough - approximation of "bare" circuit responce/behavior, not taking in account neither signal source internal resistance nor load impedance..
(just for a gross design adequacy estimation..)

When more accuracy is needed or when In & Out impedance should be taken into account (e.g. in case of load impedance being less than 10 times Emitter resistance and/or signal source impedance being more than 10 times (h_FE*R_E)//bias circuit resistance), calulations should be performed in a more in depth extend..

e.g.
R_E' = R_E//R_L
Gain = R_E'/[R_E' + r_e + (Z_source/h_FE)]
Input impedance = h_FE(R_E' + r_e)
Output impedance = Z_source/h_FE + r_e

For FET device you can use 1/g_m instead of r_e

[PRR]

Simple followers inevitably have gain less than unity. Enough to notice? It depends.

Changing the FET does little. Gm is related to current and device area. The very few very large area devices made are optimized for high current, you need a low-R source resistor to make that happen, so gain hardly changes.

A 19 cent chip opamp will give gain of 0.999+ over the audio band simply.

There's usually losses in bias resistors, and input and output protection, which can easily approach 5%. An advantage of the chip opamp that that we *can* trim the gain to say 1.05 and ensure over-unity gain for all likely conditions. And sensitive musicians will usually hear even a small level change, and prefer the slightly louder signal. This makes your buffer "better than a short wire" even if it does nothing else to the sound.

If you truly hear the small distortion of a JFET and want it, you can follow a JFET with a chip wired for gain of 1.1.