Companion Fuzz with contour & blend controls

[dthurstan]

Hi Antonis

Yeah, they are 2N3904. I have different batches of 2N3904, I think they are ~230. I did but ones in which all had roughly similar gains. I know you should use low gains (i.e. ~100) for Q1 & Q2, but I didn't.

[antonis]

I asked in particular for Q3 gain due to rather voltage divider base bias high value resistors..
For a gain of 230 you have a Base reflected Emitter resistance (transistor input impedance) slightly higher than 900k [230 X (3k9+re)]....
For a rounded calculation let's say it's 1M..
That resistance is effectivelly set in parallel with R9 resulting into 500k for lower divider leg so Base is actually biased at 3V and Emitter at about 2.4V..
For Balance pot set midway, 5k are set in parallel with 3k9 resulting into 2k2 Emitter load..
(for lower pot settings, things are getting worse..)

Emitter followers are inherently non-linear devices - they can source plenty of current but the can only sink limited current (set by Emitter/Load ratio..)
e.g. for Emitter & Load resistors of equal value, positive waveform can go up to 9V  but negative waveform can only go down to 2.25V, considering 4.5V Emitter quiescent voltage.. (ignoring V_CEsat & less than unity voltage gain..)
So, for a summetrical output, Emitter should be biased higher than mid-supply (at 5.6V, instead of present 2.4V, for an equal swing of 3.37V..)

To make long story short, Q3 gain should be at least 10 times higher (or R8 & R9 values ten times lower) and ratio of R9/R8 = 2.3..
(of course, all the above don't count much for signals of less than 2V peak amplitude..)

[dthurstan]

I was using Jack Orman's basic buffers as a guide. Hence the 10uF C10. I figured the parallel of 1M & 1M would give me closer to 500k  . I calculate the input impedance of ~320k. With lower R8 & R9 values and a 2.3 ratio. I get R9 220k, R8 95k & input impedance of 60k.

If I increase R10 to 10k keep R8 & R9 at 1M, input impedance would be ~410k.

[antonis]

I don't think (or ever found..) that Jack should use 1M/1M  resistors for  ordinary BJT (not Darlington) biasing..

BJTs biasing configuration dominates significantly overall input impedance due to 10/1 divider/base currents rule of thumb..
(the bigger the ratio the more stiff the divider but also the more lower the divider resistor values, for a given current gain & Emitter resistor)

There are plenty of techniques for raising input impedance (like divider bootstrapping, current source & bootstrap drive stage, Darlington w current source & Collector bootstraped, etc) but an JFET Source follower might be the easiest (laziest) solution..

[dthurstan]

Hi Antonis, your right, Jack shows a 220k/220k network.

I have tried to read up on transistor stages, I think I know what I'm doing then people point out issues. It's all learning I guess. But could you recommend a good book on understanding transistor electronics/design? I've got Paul Horowitz, The Art of Electronics and I read articles on www.electronics-tutorials.ws. But there is a lot holes in my knowledge.

[antonis]

Holes are in everyone's knowledge..
(same stands for electrons, I presume - unless knowledge is unipolar..)

Art of Electronics is a very good textbook with the lesser amount of maths so keep studing it..