Troubleshooting help please

[Grubb]

Hi folks. I built a friend a 2-in-1 distortion and boost on a custom PCB I designed. On testing, the LEDs come on for both channels, and the boost effect works perfectly. The distortion side passes sound when bypassed, but when activated, sound is lost. There are no obvious visual issues.

I traced the signal with an audio probe and found a point early in the circuit at which the signal is severely reduced. Am I right in thinking an IC buffer should not experience a large signal drop? Pin 3 on the IC has plenty of signal, but there's not much audio if any at Pin 2 or 1.


I have tried different TL072 chips in this socket and there's little difference (I can hear a tiny signal on some and almost no signal on others). Some advice about what to do next would be greatly appreciated.

[ElectricDruid]

What's "VA" as opposed to "Vref"? Both inputs of the Op-amp need to be biased to the same voltage. How is the op-amp powered? (I know, but people forget...)

Aside from those two things, yes, it looks like it should work. It's a simple non-inverting buffer with a little bit of gain - a good solid input stage for a pedal.

[Grubb]

I'm guessing people will ask for more info. Here's the schematic for this effect:


Voltages:
Supply: 9v (1Spot CS12)

D4
A: 9.22V
K: 9.01V

IC2
P1 - 1.181V
P2 - 1.180V
P3 - 0.784V
P4 - 0V
P5 - 1.176V
P6 - 1.119V
P7 - 1.169V
P8 - 1.642V

IC3
P1 - 1.183V
P2 - 1.155V
P3 - 1.180V
P4 - 0V
P5 - 1.180V
P6 - 1.181V
P7 - 1.181V
P8 - 1.642V

IC4
P1 - 1.165V
P2 - 1.157V
P3 - 1.175V
P4 - 0V
P5 - 0.824V
P6 - 1.180V
P7 - 1.180V
P8 - 1.642V

These all seem way too small. I'm thinking R4 should be 10R, not 10K 

EDIT: I checked the original schematic I was copying from and yep, R4 is supposed to be 10R. Hopefully a simple fix in that case.

[antonis]

Definatelly, R10 should be 10R (or so) or else V_CC should be about 6V..
(hence V_REF about 3V..)

Plz check R4, R6 & R7 actuall values 'cause either R4 is 1M or R6/R7 are 1k..

So, V_REF is actually a "regulated" V_A..

Some circuit improvements:
Place a cap in series with R30
Delete C12 or place a bias resistor from V_REF to pin 5 of IC2.2 (amp is unbiased..!!) (edited)
Place a cap between IC3.1 pin 1 and R18

[antonis]

I'd also suggest to keep V_REF as "clean" as possible, by routing all unnecessary connections (e.g. R30, TIGHT pot, D4/D5 pair) to GND..
(obviously, you'll need a cap before D4/D5 and a bias resistor for IC4.1)