What do you think would work best?

[fryingpan]

I actually did do an analysis with a 1000H inductor in series with the 6.8k resistor and it appears to be stable with both caps in as mentioned.

The Tian method is the only method which provides the exact result.   All the other methods are approximations.  If you break the loop at the right point you can get usable results in most (but not all cases) using the approximate methods.   If you look at your original thread from some months back I mentioned voltage and current injection.  These have less problems than the inductor method but are still approximations.  I think I posted Tian vs current injection in that old thread.   You can see how one is an approximation but still usable (in that case).

https://www.diystompboxes.com/smfforum/index.php?topic=132374.msg1289176#msg1289176

If you don't have inductance in the supply lead and/or capacitive loads those amplifiers tend to be stable.  If you have long leads with say 1uH inductance on the +ve rail things can change quickly.  Similarly for capacitive loads.  For a preamp on a PCB you can often ignore the capacitive load case but there can be cases where 10pF capacitive load has an effect on stability.

If you intend on using a feedback cap in the final design then you should do the stability analysis with the feedback cap present.  It does change things because the loop gain will *increase* at high frequencies with the cap present.   (If you use the feedback cap to help stability, like in a wideband amp then that's a whole different game and the choice of the feedback cap is to help improve the phase margin; essentially adding phase lead compensation.)

Have a look at my previous post, I did take your advice into account and evaluated stability through Tian's method. I still don't understand why the simulation shows ringing at the step response if feedback is reduced (gain is increased) by a certain amount.

[Rob Strand]

Have a look at my previous post, I did take your advice into account and evaluated stability through Tian's method. I still don't understand why the simulation shows ringing at the step response if feedback is reduced (gain is increased) by a certain amount.

I suspect what you are seeing is actually the downward tilt on the plateau of the square-wave pulse.    That's not ringing or overshoot.    When you pass a squarewave through a high-pass filter the top of the square-wave tilts down.  You can do a simulation with a simple RC high-pass filter.   The high-pass filter comes from the input cap on the amplifier and the bass-cap in the feedback loop.  Your pulse width is very long, like 100ms, so you see a tilt.  If you increase your square-wave frequency to 1kHz (width 500us, period 1ms) the tilt should largely disappear then you can see the overshoot.

When you check for ringing/overshoot you need to make the pulse amplitude small enough that the amplifier doesn't clip.    You can check what happens for large signals but that's a different thing.   You might already be aware that overshoot is related to the phase-margin; higher phase-margins are more damped and overshoot less.   You would check for overshoot on the emitter of Q3 as the post Q3 low-pass filter
will reduce the observed overshoot.

When you do the Tian's method simulation you *must* set the input signal level to zero (ie. AC 0), or alternatively you can ground the input.   To ground the input you replace the source with a short to ground and leave all input components like the 100ohm input resistor and the input cap connected to the circuit.  If you have other AC sources present for the Tian's method simulation it will completely corrupt the results.   The method has it's own voltage and current source which it uses one at a time to get two simulation results; that's the @1 and @2 in the variables when you plot the loop gain.
If you aren't seeing tilt on the squarewave perhaps post your sim results with a plot and the gain pot setting and I'll try to recreate the same behaviour.

[fryingpan]

Have a look at my previous post, I did take your advice into account and evaluated stability through Tian's method. I still don't understand why the simulation shows ringing at the step response if feedback is reduced (gain is increased) by a certain amount.

I suspect what you are seeing is actually the downward tilt on the plateau of the square-wave pulse.    That's not ringing or overshoot.    When you pass a squarewave through a high-pass filter the top of the square-wave tilts down.  You can do a simulation with a simple RC high-pass filter.   The high-pass filter comes from the input cap on the amplifier and the bass-cap in the feedback loop.  Your pulse width is very long, like 100ms, so you see a tilt.  If you increase your square-wave frequency to 1kHz (width 500us, period 1ms) the tilt should largely disappear then you can see the overshoot.

When you check for ringing/overshoot you need to make the pulse amplitude small enough that the amplifier doesn't clip.    You can check what happens for large signals but that's a different thing.   You might already be aware that overshoot is related to the phase-margin; higher phase-margins are more damped and overshoot less.   You would check for overshoot on the emitter of Q3 as the post Q3 low-pass filter
will reduce the observed overshoot.

When you do the Tian's method simulation you *must* set the input signal level to zero (ie. AC 0), or alternatively you can ground the input.   To ground the input you replace the source with a short to ground and leave all input components like the 100ohm input resistor and the input cap connected to the circuit.  If you have other AC sources present for the Tian's method simulation it will completely corrupt the results.   The method has it's own voltage and current source which it uses one at a time to get two simulation results; that's the @1 and @2 in the variables when you plot the loop gain.

No, no. I know that the sloping response to a step function is merely a consequence of the high pass filter. The amplifier actually rings (and I just realised, when it's clipping). Here, I'll show you.



I stopped the simulation after a few us because it actually slows to a crawl, but you can clearly see the gross ringing.






There is no ringing (but a weird kink in the response) if I add a resistor greater than 62 ohms in series to the 68p capacitor.



The kink goes away if the resistor is made larger (here, with 100 ohms).



Here, with a 0.1V step at the input. No ringing.



Or even with a 1V input (so, technically clipping) but a shorter "on" time.



So I'm assuming it's a bug, rather than actual instability.
All of this does not happen with gain lower than a certain amount.
Anyway, just in case, I added in that 100 ohm resistor. It's harmless after all.

Also, I did the Tian analysis with no AC input (I disconnected the voltage generator and grounded it).

[Rob Strand]

No, no. I know that the sloping response to a step function is merely a consequence of the high pass filter. The amplifier actually rings (and I just realised, when it's clipping). Here, I'll show you.

Very interesting. 

First off, I do see what you see.

So to me I wouldn't say that's ringing I'd say it's outright oscillating.   The question is why?

So I'm assuming it's a bug, rather than actual instability.
All of this does not happen with gain lower than a certain amount.
Anyway, just in case, I added in that 100 ohm resistor. It's harmless after all.

Well, there's more to the story of stability:

If the output stage itself is oscillating, called parasitic oscillation, it won't show up on the loop-gain plot.   If you imagine a stable amplifier where someone injects a 10MHz signal into the innards of the amplifier then you will see 10MHz come out.   That's kind of what happens with parasitic oscillation.   The output stage itself forms an oscillator.

Another reason is a little more difficult to visualize.  When you do a stability analysis you are doing it at the bias point (in your case 18V supply and output biased at ~10V).   When an amplifier is processing a real signal the output stage swings from 0V to 18V.  When it does that the currents and voltages in all the parts vary.  That causes capacitance and gain of the amplifier stages to change from the bias point values.   So what can happen is at some output voltage and current the loop gain can become unstable.   I often check the stability at different bias points by injecting DC into the input, or something equivalent.

Off the bat I don't know what the exact cause is.

Initially I suspected parasitic oscillation so I added a 1k resistor between the collector of Q2 and the base of Q3, a common technique to suppress parasitic oscillation, and it worked.

I also tried moving the feedback point from Q3's emitter to Q2's collector and that worked.   It's easy to think the phase-shift at the output stage is cause loop-instability.  However, by moving the feedback point the Q3's base is driven by a low impedance so that might be the reason it fixes the oscillation.

Then there's your results where making small changes also suppressed the oscillation.

More work is required to work out what is going on!!

Also, I did the Tian analysis with no AC input (I disconnected the voltage generator and grounded it).

In one of your previous pics you grounded the output of the source, which isn't correct, so I wasn't sure if you grounded the *input of the amplifier* or not.

[fryingpan]

The reason I say that I suspect it is a bug in the simulation is that by merely changing the input signal's *length* there is no oscillation. I might understand if I changed any other parameter (rise time, voltage, etc.) but the oscillation triggers at the step's onset, not afterwards. It doesn't make much sense that a shorter "on" time doesn't cause oscillation (it would violate causality). Nevertheless, if the simulation complains, I always suspect something must be close to instability, therefore it is best to make some change.

[Rob Strand]

The reason I say that I suspect it is a bug in the simulation is that by merely changing the input signal's *length* there is no oscillation. I might understand if I changed any other parameter (rise time, voltage, etc.) but the oscillation triggers at the step's onset, not afterwards. It doesn't make much sense that a shorter "on" time doesn't cause oscillation (it would violate causality). Nevertheless, if the simulation complains, I always suspect something must be close to instability, therefore it is best to make some change.

You could be right.   There's something abnormal going on.

I just removed all my fixes and tried to put it back to the initial failing state and I could not get it to oscillate at all.   Once the pulse goes high it does suffer some slow convergence.

After that I exited LTSpice and restarted it and get a small region of oscillations but relatively fast convergence!   The oscillations have period 37.8ns (26.5MHz).   My .tran statement is

.tran 0 150m 0

I normally add a maximum step of 1us to 10us.  Sometimes playing with the step helps or avoids weird cases.
.tran 0 150m 0 1u

When I see weird problems and slow convergence I will often change the transistor models.   Given we can change one or two parts and the problem goes away I've been reluctant to do this for this problem.

[Rob Strand]

FYI,
- Different transistor models -> no change
- replace Q3 with an ideal current controlled current source -> no change (over a wide range of gains 100 to 10000)
- decreased 2.2n cap on output to 2.2f (tiny) -> oscillation removed
- increased output series resistor from 240 to 2400 (leave 2.2n cap) -> still oscillates
  A little weird as this is also disconnecting the 2.2nF cap.
- output series resistor 2400 and Q2 collector resistor 12k
  .tran 0 150m 0  ->   low level oscillation over entire waveform past 110ms; approx 290us period
  but
  .tran 0 150m 0 50u  ->  short region of oscillation with period 100us (ie. 2x50us ==> very suspicious)
  .tran 0 150m 0 10u  ->  short region of oscillation with period 20us (ie. 2x10us ==> very suspicious)

So either there is very high frequency oscillation and the time step is aliasing it, or,
the time step itself is causing a fake/numerical oscillation.

[Rob Strand]

It seems the cause of the oscillation problem is quite difficult to pin down and could take a whole day to solve.

I've managed to at least identify what triggers the problem:  when Q2 saturates enough to cause it's VCE voltage to be less than around 25mV to 30mV we see a burst of oscillation.   I've got the gain pot set at 0,1 (500 ohm).   To me it seems real and almost systematic when the conditions are correct.

The oscillation frequency is in the 14MHz to 30MHz region.   If the transient analysis time steps are too long, or unspecified, an alias effect is seen and the spice output will show a lower oscillation frequency.   If we force a maximum time step of less than 35ns it seems to produce a consistent output.  (To reduce simulation times I suggest reducing the delay on the pulse.)

I had an idea why the oscillation occurs but haven't fully explore it:  If you imagine Q2 is saturated the collector voltage of Q2 is more or less pinned to the emitter.    However, the collector current of Q1 can can still feed into the 100 emitter resistor and cause some variation on the collector voltage of Q2.   When that occurs the signal on the Q2's collector is the wrong phase because Q2 no longer inverts the signal.   The idea falls apart when we look at the loop gain *at a point where Q2 is biased into saturation*.  When Q2 saturates the loop gain drops because Q2 doesn't provide much gain in saturation.   As a result the loop gain appears to be less than one.   However what does look suspicious is the peak gain occurs around 20MHz, which is around the oscillation frequency.   The phase is only -120deg or so.   So either I'm on the wrong track or there's more to it.  For example it could be the linear loop-gain analysis isn't enough to see some sort of complex non-linear oscillations.

[fryingpan]

At this point, I wonder whether that 100 ohm resistor is really solving the issue. Probably the 1k resistor from Q2e to Q3b is a better choice?

[Rob Strand]

At this point, I wonder whether that 100 ohm resistor is really solving the issue. Probably the 1k resistor from Q2e to Q3b is a better choice?

Yes it crossed my mind as well.

In the light of the phase inversion idea I like the 100 ohm in series with the feedback cap.  In the case of Q2 saturation, if we consider the gain of the first transistor as the ratio of the emitter resistor of Q2, which is 100 ohm, to the added 100 ohm in the emitter of Q1 then that means the under saturation the gain is probably less than 1 --> so no oscillations.   It's at bit of a loose argument though.

The fact the output 2n2 cap to ground and the 1k Q2e to Q3b have an effect seem to me they are just pushing some existing mechanism over the edge one way or the other.   At this point I've ruled out parasitic oscillation of Q3 because I can replaced it with an ideal (infinite bandwidth) current controlled current source with a very high current gain and the oscillation is still there.

That's the trouble with not understanding what's going on.  We can only speculate a solution.